Speaker
Valerio Nappi
(CERN)
Description
Real-time control algorithms for power converters in particle accelerators require flexible platforms capable of high iteration rates (up to 100 kHz).
This work evaluates the suitability of the Zynq UltraScale+ SoC (A53 cores) for such applications. After characterizing the access time of the most basic FPGA-CPU access path, we show how this path is unsuitable for real time controls. We then propose an alternative system, characterizing the critical metrics: PL access, Memory access, ACP latency performance, and Interrupt latency. We identify a suitable data path for real time controls and propose an exploitation paradigm for achieving reliable sub-microsecond latency.
| Talk's Q&A | End of talk |
|---|---|
| Talk duration | 20'+10' |
| Will you be able to present in person? | Yes |
| If we are unable to accommodate your oral presentation, would you be willing to consider presenting a poster instead? | Yes |
Author
Valerio Nappi
(CERN)