May 27 – 29, 2026
CERN
Europe/Zurich timezone
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A Multigigabit Link Layer Protocol for Single Picosecond Latency Determinism Using AMD Ultrascale+ GTH and GTY Transceivers

May 29, 2026, 9:45 AM
25m
500/1-001 - Main Auditorium (CERN)

500/1-001 - Main Auditorium

CERN

400
Show room on map
Talk Solutions to everyday digital design problems Solutions to everyday digital design problems

Speaker

Paul Bachek (Brookhaven National Lab)

Description

Precision timing distribution systems require deterministic and repeatable high speed serial data link latency. The EIC Timing Data Link will employ a specialized link layer protocol for deterministic multigigabit communication using AMD Ultrascale+ GTH and GTY transceivers. Link latency must also be measurable to accurately compensate in real time for latency variations of the physical medium. The point-to-point link is full duplex and fully synchronous with a latency control algorithm to align the internal clocks of each system with picosecond resolution. Deterministic clock domain crossing between systems is ensured using static timing analysis of the elastic buffer control signals.

Talk's Q&A During the talk
Talk duration 20'+10'
Will you be able to present in person? Yes
If we are unable to accommodate your oral presentation, would you be willing to consider presenting a poster instead? Yes

Author

Paul Bachek (Brookhaven National Lab)

Presentation materials