Speaker
Description
FPGAs excel in ultra low latency tasks like AI decisions and high speed trading, but the choice between traditional HDL (Verilog/VHDL) and High Level Synthesis (HLS) remains debated. HDL provides precise control for maximum clock speeds Fmax and minimal resources, while HLS accelerates development by converting high level C++ code to hardware.
This comprehensive benchmarking uses industry tools to compare performance across compute intensive, visual processing, communication, and system level workloads.
Recent 2024-2025 tools make HLS power competitive. LLM generated Verilog shows 85\% functional correctness, validated by synthesis. Ongoing work explores domain specific FPGA architectures, modifying routing fabrics and logic blocks based on workload needs for optimal performance and lowest power.
| Talk's Q&A | End of talk |
|---|---|
| Talk duration | 15'+7' |
| Will you be able to present in person? | Yes |
| If we are unable to accommodate your oral presentation, would you be willing to consider presenting a poster instead? | Yes |