Speaker
Description
According to Wilson Verification Survey, FPGA verification engineers spend 47% of their time debugging. This is no wonder as OSVVM's test suite produces log files that have 1.4M lines. Just sifting through the wealth of information and identifying the source of problems quickly is a challenge.
To help, many approaches, including OSVVM, provide a JUnit XML based report (CI likes these) and a log file.
OSVVM takes reporting further. OSVVM provides an HTML based build summary with VHDL test information (rather than Java) and includes links to details, such as test case reports, log files (HTML and text), requirement reports, and code coverage reports. OSVVM's test case reports contain detailed alert, functional coverage, and scoreboard statistics as well as links to the HTML log (jumping to this test case's results) and VHDL test case file (open in vscode or browser).
With OSVVM, reporting is automatic and finding test information is just a click away.
| Talk's Q&A | End of talk |
|---|---|
| Talk duration | 25'+12' |
| Will you be able to present in person? | Yes |