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3rd FPGA Developers' Forum (FDF) meeting

May 27 – 29, 2026
CERN
Europe/Zurich timezone
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Session

Sharable HDL cores

May 27, 2026, 4:15 PM
500/1-001 - Main Auditorium (CERN)

500/1-001 - Main Auditorium

CERN

400
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Conveners

Sharable HDL cores

  • Filiberto Bonini (CERN)

Presentation materials

There are no materials yet.

  1. 105. Scalable and lightweight RoCEv2 TX FPGA IP core
    Gabriele Bortolato (Universita e INFN, Padova (IT))
    5/27/26, 4:15 PM
    Sharable HDL cores
    Talk

    In many Data Acquisition (DAQ) systems, a significant portion of CPU resources is spent on networking rather than actual data processing. One way to reduce this overhead is to implement Remote Direct Memory Access (RDMA) directly in FPGA logic. Offloading RDMA to hardware can increase throughput, reduce latency, and significantly lower CPU utilization on the receiver side. This talk presents a...

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  2. 154. The PoC-Library - Free and Open-Source VHDL IP Core Library
    Patrick Lehmann (PLC2)
    5/27/26, 4:45 PM
    Sharable HDL cores
    Talk

    The PoC-Library

    The PoC-Library (Pile of Cores) is a free and open-source IP core library published since 2015 under Apache License, 2.0. It offers abstraction layers like the on-chip RAM modules (OCRAM) to abstract from device technologies, architectures and vendors. Therefor, the PoC-Library is independent from ASIC or FPGA, Altera or AMD/Xilinx devices or EDA toolchain.

    Thís...

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  3. 132. NDK framework: Deep-Diving into High-Throughput Network Monitoring Pipelines
    Daniel Kondys (CESNET)
    5/27/26, 5:25 PM
    Sharable HDL cores
    Talk

    The Network Development Kit (NDK) is an open-source framework for high-speed FPGA network applications. Following up on last year’s overview and feature set, this presentation dives into the technical implementation and specific design challenges of building 400 GE network monitoring probes.
    Monitoring probes perform wire-speed protocol parsing, traffic filtering, packet marking, and flow...

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  4. 76. USB implementation with GateMate FPGA
    Anton Kuzmin (gmm7550)
    5/27/26, 6:00 PM
    Sharable HDL cores
    Talk

    GateMate FPGA from Cologne Chip [1] is natively supported by FOSS development tools (Yosys and nextpnr). The GateMate FPGA has a transceiver capable of communication at 5&nbsp Gbps. However, no open and free USB 3.x core is available for it. I'm running a project to implement a USB on the GateMate FPGA.

    A hardware platform [2] (FPGA module and an adapter board) is designed, produced, and...

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