3rd FPGA Developers' Forum (FDF) meeting

Session

Solutions to everyday digital design problems

May 29, 2026, 9:00 AM

500/1-001 - Main Auditorium (CERN)

Conveners

Solutions to everyday digital design problems: 1

• Paschalis Vichoudis (CERN)

Solutions to everyday digital design problems: 2

• Evangelia Gousiou (CERN)

100. The CERN Open Hardware Licence for FPGA Designs

Javier Serrano (CERN)

5/29/26, 9:00 AM

Solutions to everyday digital design problems

Talk

Version 2 of the CERN Open Hardware Licence was published in 2020 and approved by OSI in 2021. During its drafting, a great deal of thought and discussions were devoted to catering for the specificities of IC and FPGA design. The licence comes in three variants in order to give these communities appropriate tools for sharing in the three usual regimes: permissive (P), weakly-reciprocal (W) and...

124. Kyokko2: a portable multi-gigabit serial communication controller

Sou Tanaka (Osana Lab)

5/29/26, 9:25 AM

Solutions to everyday digital design problems

Talk

This work proposes a synchronous version of Kyokko, a vendor-independent serial communication IP. Kyokko is our open-source implementation of Aurora 64B/66B and separates the device-independent protocol layer from the device-specific transceiver interface, enabling portability across multiple FPGA vendors. The original Kyokko design requires a 64:66 asynchronous gearbox on the FPGA's...

88. A Multigigabit Link Layer Protocol for Single Picosecond Latency Determinism Using AMD Ultrascale+ GTH and GTY Transceivers

Paul Bachek (Brookhaven National Lab)

5/29/26, 9:45 AM

Solutions to everyday digital design problems

Talk

Precision timing distribution systems require deterministic and repeatable high speed serial data link latency. The EIC Timing Data Link will employ a specialized link layer protocol for deterministic multigigabit communication using AMD Ultrascale+ GTH and GTY transceivers. Link latency must also be measurable to accurately compensate in real time for latency variations of the physical...

95. Latency analysis of the CPU-FPGA interface in the Zynq UltraScale+ SoC

Valerio Nappi (CERN)

5/29/26, 10:40 AM

Solutions to everyday digital design problems

Talk

Real-time control algorithms for power converters in particle accelerators require flexible platforms capable of high iteration rates (up to 100 kHz).
This work evaluates the suitability of the Zynq UltraScale+ SoC (A53 cores) for such applications. After characterizing the access time of the most basic FPGA-CPU access path, we show how this path is unsuitable for real time controls. We then...

166. Recovered Clock Phase Monitoring on AMD Transceivers for Deterministic Timing

Nikitas Loukas (University of Notre Dame (US))

5/29/26, 11:05 AM

Solutions to everyday digital design problems

Talk

After the Phase-II upgrade of the Large Hadron Collider at CERN, pile-up discrimination in the CMS Electromagnetic Barrel Calorimeter demands a clock system with picosecond precision and deterministic phase. Although modern electronics can achieve sub-5 ps RMS jitter, widely used FPGAs do not ensure phase repeatability after reset. Their Multi-Gigabit Transceivers prioritize bit error rate...

148. SystemVerilog Hacks: Circumventing the Limitations of SystemVerilog

Yair Linn (TRIUMF)

5/29/26, 11:30 AM

Solutions to everyday digital design problems

Talk

SystemVerilog is a powerful language with relatively good compiler support. However, some inexplicable oversights and limitations in the SystemVerilog standard can cause HDL designers to expend significant work that would have been unnecessary had simple tweaks in the language's standard been adopted. For example, one limitation of SystemVerilog is that a "struct" cannot be parameterized more...

79. CDCs, FIFOs, and Width Converters: How to Combine Open Logic Building Blocks Correctly

Oliver Bründler (Enclustra GmbH)

5/29/26, 11:50 AM

Solutions to everyday digital design problems

Talk

In FPGA design, correctly handling clock domain crossings, buffering data streams, and matching data widths is critical for reliable and maintainable systems. The Open Logic FPGA Standard Library (open source) provides building blocks for these challenges, but many users struggle to understand when and how to combine them effectively.

This talk will walk you through the CDCs, FIFOs, and...

149. Comparing HDL and HLS: Which Wins for Ultra Fast FPGA Designs?

Abhinav Gaonkar

Solutions to everyday digital design problems

Talk

FPGAs excel in ultra low latency tasks like AI decisions and high speed trading, but the choice between traditional HDL (Verilog/VHDL) and High Level Synthesis (HLS) remains debated. HDL provides precise control for maximum clock speeds Fmax and minimal resources, while HLS accelerates development by converting high level C++ code to hardware.

This comprehensive benchmarking uses industry...