3rd FPGA Developers' Forum (FDF) meeting

Session

Algorithm Implementation

May 28, 2026, 1:35 PM

500/1-001 - Main Auditorium (CERN)

Conveners

Algorithm Implementation: 1

• N. Engelhardt (YosysHQ)
• Tom Williams (Rutherford Appleton Laboratory (GB))

111. NGRC on SoC for online learning of dynamical systems

João Folhadela (German Aerospace Center)

5/28/26, 1:35 PM

Algorithm implementation in HDL and HLS

Talk

Predicting the evolution and control of dynamic systems in real time remains a demanding task for conventional methods that depend on accurate models and intensive continuous optimization, which often breaks under uncertainty, noise or delays. Reservoir Computing (RC) provides a lightweight alternative, needing only small training sets and simple inference. We present a low‑cost, low‑power...

89. Accelerating Data: Lossless Compression for HPC, Datacenter, AI, and Scientific Data Pipelines

Calliope-Louisa Sotiropoulou (CAST)

5/28/26, 2:05 PM

Algorithm implementation in HDL and HLS

Talk

High-performance computing and data-intensive infrastructures are increasingly limited by data movement rather than processing power. Large scientific experiments such as those at CERN, together with AI training clusters and datacenters, generate continuous data streams that must be handled at multi-100 Gb/s under strict latency, power, and storage constraints. Lossless compression in FPGA or...

90. High-speed digital twins: Pushing simulation time-steps into the nanosecond range using Versal ACAP

Pablo Trujillo (controlpaths)

5/28/26, 2:35 PM

Algorithm implementation in HDL and HLS

Talk

In the design and validation of high-speed electrical systems, such as power converters, the fidelity of the electrical model is strictly limited by the minimum achievable time-step. Conventional FPGA-based simulators often operate in the range of microseconds or, at best, several hundred nanoseconds. This limitation can lead to failures in capturing high-speed transients or introduce...

147. Study of non linearities on the AMD Phase Interpolator

Edoardo Orzes (CERN)

5/28/26, 3:05 PM

Algorithm implementation in HDL and HLS

Talk

In the context of high precision timing distribution there is a growing awareness of phase instabilities. Novel solutions are relying on phase tracking and phase shifting to stabilize clocks and data streams.
AMD transceivers provide an ultra fine phase shifter (phase interpolator), with a step smaller than 2 ps, which can be controlled by the user to phase shift the transmitted data.
This...

121. Dynamic Derandomizing Buffer: A Portable and Scalable Solution for Time-Ordered Packet Aggregation

Mitja Vodnik (CERN)

5/28/26, 3:35 PM

Algorithm implementation in HDL and HLS

Talk

The Dynamic Derandomizing Buffer is a firmware design for joining time-stamped packets form multiple incoming data streams with randomly varying time-skews into a single time-ordered output stream. It is developed at CERN primarily to handle the output from the novel FastRICH ASIC (the LHCb RICH detector readout chip for Runs 4 and 5), but intentionally made agnostic to this use-case so it can...