3rd FPGA Developers' Forum (FDF) meeting

Session

Verification

May 28, 2026, 9:00 AM

500/1-001 - Main Auditorium (CERN)

Conveners

Verification: 1

• Mathieu Saccani (CERN)

85. Inside UVVM: Architecture and Design of Custom Verification Components

Markus Leiter (p2l2)

5/28/26, 9:00 AM

HDL verification and simulation tools

Talk

This talk takes an in-depth look inside a UVVM VVC, explaining its internal architecture and core design principles. Key concepts such as the command-based interface, command queue, command interpreter, and executor are explored in detail, along with synchronization mechanisms, transaction handling, and the interaction with Bus Functional Models (BFMs).

Building on this foundation, the...

158. Open-source simulation landscape and advances towards mixed language support

Augusto Fraga Giachero (CNPEM / LNLS)

5/28/26, 9:30 AM

HDL verification and simulation tools

Talk

The current scenario of HDL open-source simulators has changed significantly, raising the question of what cases traditional commercial simulators are still necessary.

GHDL and NVC are advancing quickly towards full VHDL 2008 compliance in addition to experimental VHDL 2019 support in NVC. Mixed language simulation has been a challenge with open-source tools, previous attempts used...

108. Open Source HDL Co-Simulation with AMD Alveo

Matthias Kern (p2l2)

5/28/26, 10:00 AM

HDL verification and simulation tools

Talk

HDL simulation is essential for verifying digital designs, but its computational intensity often results in slow turnaround times, delaying development cycles.
This presentation demonstrates how AMD Alveo FPGA acceleration cards, integrated with open source HDL simulators and frameworks, can dramatically speed up simulation workflows.

The presentation begins by outlining the bottlenecks in...