Name: 3rd FPGA Developers' Forum (FDF) meeting
Start: 2026-05-27T09:00:00+02:00
End: 2026-05-29T20:00:00+02:00
Location: CERN

3rd FPGA Developers' Forum (FDF) meeting

from Wednesday, May 27, 2026 (9:00 AM) to Friday, May 29, 2026 (8:00 PM)

Monday, May 25, 2026
Tuesday, May 26, 2026
Wednesday, May 27, 2026

10:00 AM CERN Campus Visits: Visits
Visits
10:00 AM - 1:00 PM

1:00 PM Conference Registration: Participant Check-in
Participant Check-in
1:00 PM - 2:00 PM
Room: 500/1-001 - Main Auditorium
2:00 PM Introduction
2:00 PM - 3:00 PM
Room: 500/1-001 - Main Auditorium
Contributions

2:00 PM Welcome to FDF26 - Davide Cieri (Max Planck Society (DE))

2:10 PM What Star Trek can teach us about using AI in FPGA design - Adam Taylor (Adiuvo Engineering)
3:00 PM Sponsor Presentations: Sponsor Presentaton
Sponsor Presentaton
3:00 PM - 3:45 PM
Room: 500/1-001 - Main Auditorium
Contributions

3:00 PM Altera - Christian Faerber (Altera)

3:03 PM AMD - Thilo Ohlemueller (AMD)

3:06 PM CAEN - Luca Colombini (CAEN)

3:09 PM CAST - Calliope-Louisa Sotiropoulou (CAST)

3:12 PM Efinix - Fabian Heinrici (Efinix)

3:15 PM iWave - Sharath Kumar (iWave)

3:18 PM Knowledge Resources - Bruno Monteiro (Knowledge Resources GmbH)

3:21 PM Lattice Semiconductor - Hardik Shah (Lattice)

3:24 PM Microchip - Jens Huettemann (Microchip Technology Munich GmbH)

3:27 PM NanoXplore - JEAN LOUIS FRIGOUL (NANOXPLORE)

3:30 PM PLC2 - Patrick Lehmann (PLC2)

3:33 PM ProDesign - Stefan Rooseboom (ProDesign)

3:36 PM Samtec - Neil Potter (Samtec) Veronique Branca (Samtec)

3:39 PM Techway - Romain Larousse (Techway)

3:42 PM Trenz Electronic - Martin Rohrmüller (Trenz Electronic)
3:45 PM Tea Break
Tea Break
3:45 PM - 4:15 PM
Room: 500/1-001 - Main Auditorium
4:15 PM Sharable HDL cores
4:15 PM - 6:30 PM
Room: 500/1-001 - Main Auditorium
Contributions

4:15 PM Scalable and lightweight RoCEv2 TX FPGA IP core - Gabriele Bortolato (Universita e INFN, Padova (IT))

4:45 PM The PoC-Library - Free and Open-Source VHDL IP Core Library - Patrick Lehmann (PLC2)

5:25 PM NDK framework: Deep-Diving into High-Throughput Network Monitoring Pipelines - Daniel Kondys (CESNET)

6:00 PM USB implementation with GateMate FPGA - Anton Kuzmin (gmm7550)
6:30 PM Group Photo
Group Photo
6:30 PM - 6:40 PM
Room: 500/1-001 - Main Auditorium
7:00 PM Poster Session and Welcome Reception: Posters are on display throughout the workshop. During the poster session, participants are free to browse at their own pace (no dedicated timeslot per poster; listed in Indico for reference only).
Posters are on display throughout the workshop. During the poster session, participants are free to browse at their own pace (no dedicated timeslot per poster; listed in Indico for reference only).
7:00 PM - 8:00 PM
Room: 500/1-001 - Main Auditorium
Contributions

7:00 PM RoCE-Stream -- offloading (debug) data over 100Gbit RoCE RDMA - Alexander Daum (p2l2)

7:01 PM CI-Driven FPGA ML Experimentation: Unified Results from HLS, Implementation, and On-Hardware Testing - Georgios Flengas (CERN)

7:02 PM XiBIF: A Python tool and hardware platform for streamlined FPGA development - Janik Witzig (Ostschweizer Fachhochschule) Lukas Leuenberger (Ostschweizer Fachhochschule)

7:03 PM Progressive Arithmetic Optimizations : Tensor and DSP Kernels to Synthesizable Datapaths - Louis Ledoux (INSA, INRIA)

7:04 PM Emulation of classic CPUs - a SoC-centric hybrid approach - Volker Urban (Ingenieurbüro Dipl.-Ing. Volker Urban)

7:05 PM Benchmarking Neural Network Inference on Versal ACAP AI Engines for Real-Time Detector Alignment - Haider Abidi (Brookhaven National Laboratory (US))

7:06 PM Leveraging HBM for accelerating arbitrary Quantum Simulation on AMD Alveo platforms - Marwin Kirchhofs

7:07 PM Towards a predictable toolchain dedicated to the generation of FPGA circuits for control algorithms - Inès Winandy (ENAC)

7:08 PM Qualifying FPGAs for Radiation-Tolerant Applications - Patrick Urban (Cologne Chip AG)

7:09 PM An Hardware Emulator for the ATLAS Phase-II L0MDT Trigger System - Marcel Marques Boonen (Max Planck Society (DE))

7:10 PM Deep Memory for the Data Acquisition of the IceCube-Gen2 Surface Array - Frederik Schmitt (Karlsruhe Institut of Technology)

7:11 PM Practical Implementation of Lightweight Cryptography on FPGAs: Design Trade-offs, Side-Channel Considerations, and Integration Lessons - Pradeep Kumar Mohanty (NIT Rourkela)

7:12 PM POEMMA Balloon with Radio experiment as a use case for RFSoC in Astroparticle Physics - Alexander Novikov (University of Delaware)

7:13 PM Transitioning to Modern FPGA Architectures in a High-Throughput Research Facility - Bruno Fernandes (Eur.XFEL (European XFEL))

7:14 PM Geant4-driven realistic waveform generation for FPGA algorithm verification in radiation detector readout - Handan YILMAZ (istanbul technical University)

7:15 PM Resource-Efficient Streaming Beam Reconstruction on an Intel Max 10 FPGA - Liqing Qin (Heidelberg Ion Beam Therapy Centre)

7:16 PM JEDI-linear: Fast and Efficient Graph Neural Networks for Jet Tagging on FPGAs - Zhiqiang Que (University of Bristol)

7:17 PM Reconciling Fixed-Frequency Clocking and Variable Sampling-Rate Data: Real-Time Arbitrary Resampling for Stream Processing - Javier Galindo Guarch (Aragon Institute of Technology Itainnova (ES))

7:18 PM Low-Complexity Median Algorithm in FPGA for AMS-02 Layer-0 Upgrade - Luca Russo (Universita e INFN, Perugia (IT))

7:19 PM AI Inference in FPGAs for both Standard and Safe & Dependable Applications - David Ganz (ZHAW)

7:20 PM SVN is better than GIT for FPGA development: I will die on this hill - Yair Linn (TRIUMF)

7:21 PM Using native libraries functions from VHDL with VHPIDIRECT - Augusto Fraga Giachero (CNPEM / LNLS)

7:22 PM MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks - Maryam Eslami (Ruhr-Universität Bochum)

7:23 PM PandA-Bambu Backend for hls4ml - Nicolo Ghielmetti (CERN)

7:24 PM From C/C++ to Hardware with Bambu: An Open-Source HLS Research Tool - Tommaso Fellegara (Politecnico di Milano)

7:25 PM ARTEMIS: FPGA-based AD in the ATLAS Level-1 Trigger - Paula Martinez Suarez (CERN)

7:26 PM Implementation of Elias deterministic extractor for true random number generation - Lorenzo Borella (Universita e INFN, Padova (IT))

7:27 PM The Firmware Development Kit (FDK) - Adam Lee Barcock (Science and Technology Facilities Council STFC (GB))

7:28 PM Frame Buffering Design Strategies for Boosting Mobipix 15D X-Ray Imaging Rates - Allan Borgato (LNLS)
Thursday, May 28, 2026
9:00 AM Verification: 1
1
9:00 AM - 10:30 AM
Room: 500/1-001 - Main Auditorium
Contributions

9:00 AM Inside UVVM: Architecture and Design of Custom Verification Components - Markus Leiter (p2l2)

9:30 AM Open-source simulation landscape and advances towards mixed language support - Augusto Fraga Giachero (CNPEM / LNLS)

10:00 AM Open Source HDL Co-Simulation with AMD Alveo - Matthias Kern (p2l2)
10:30 AM Coffee break
Coffee break
10:30 AM - 11:00 AM
Room: 500/1-001 - Main Auditorium
11:00 AM AI: 1
1
11:00 AM - 12:35 PM
Room: 500/1-001 - Main Auditorium
Contributions

11:00 AM AMD Embedded AI Solutions - Thomas Gmeinder (AMD)

11:45 AM KalEdge-Lite: Hardware-Aware ML-to-FPGA Deployment with Automated hls4ml Integration - Romina Soledad Molina (kaleidoforge)

12:05 PM HGQ: High Granularity Quantization for Real-time Neural Networks and LUT-Based Inference - Chang Sun (California Institute of Technology (US))
12:35 PM Lunch
Lunch
12:35 PM - 1:35 PM
Room: 500/1-001 - Main Auditorium
1:35 PM Algorithm Implementation: 1
1
1:35 PM - 4:05 PM
Room: 500/1-001 - Main Auditorium
Contributions

1:35 PM NGRC on SoC for online learning of dynamical systems - João Folhadela (German Aerospace Center)

2:05 PM Accelerating Data: Lossless Compression for HPC, Datacenter, AI, and Scientific Data Pipelines - Calliope-Louisa Sotiropoulou (CAST)

2:35 PM High-speed digital twins: Pushing simulation time-steps into the nanosecond range using Versal ACAP - Pablo Trujillo (controlpaths)

3:05 PM Study of non linearities on the AMD Phase Interpolator - Edoardo Orzes (CERN)

3:35 PM Dynamic Derandomizing Buffer: A Portable and Scalable Solution for Time-Ordered Packet Aggregation - Mitja Vodnik (CERN)
4:05 PM Tea Break
Tea Break
4:05 PM - 4:35 PM
Room: 500/1-001 - Main Auditorium
4:35 PM HDL Development Tools: 1
1
4:35 PM - 6:30 PM
Room: 500/1-001 - Main Auditorium
Contributions

4:35 PM Tools and libraries Review - Francesco Gonnella (University of Birmingham (GB))

5:05 PM VHDL-LS - A Free and Open Source Language Server for VHDL - Lukas Scheller (KIT)

5:40 PM fwk: An Open-Source Framework for Standardized FPGA Development at DESY - Cagil Gumus (DESY)

6:00 PM DevOps for FPGA 101: from version control to hardware-in-the-loop testing - Matteo Vit (Starware Design)
7:15 PM Social Dinner
Social Dinner
7:15 PM - 10:35 PM
Room: 500/1-001 - Main Auditorium
Friday, May 29, 2026
9:00 AM Solutions to everyday digital design problems: 1
1
9:00 AM - 10:10 AM
Room: 500/1-001 - Main Auditorium
Contributions

9:00 AM The CERN Open Hardware Licence for FPGA Designs - Javier Serrano (CERN)

9:25 AM Kyokko2: a portable multi-gigabit serial communication controller - Sou Tanaka (Osana Lab)

9:45 AM A Multigigabit Link Layer Protocol for Single Picosecond Latency Determinism Using AMD Ultrascale+ GTH and GTY Transceivers - Paul Bachek (Brookhaven National Lab)
10:10 AM Coffee break
Coffee break
10:10 AM - 10:40 AM
Room: 500/1-001 - Main Auditorium
10:40 AM Solutions to everyday digital design problems: 2
2
10:40 AM - 12:20 PM
Room: 500/1-001 - Main Auditorium
Contributions

10:40 AM Latency analysis of the CPU-FPGA interface in the Zynq UltraScale+ SoC - Valerio Nappi (CERN)

11:05 AM Recovered Clock Phase Monitoring on AMD Transceivers for Deterministic Timing - Nikitas Loukas (University of Notre Dame (US))

11:30 AM SystemVerilog Hacks: Circumventing the Limitations of SystemVerilog - Yair Linn (TRIUMF)

11:50 AM CDCs, FIFOs, and Width Converters: How to Combine Open Logic Building Blocks Correctly - Oliver Bründler (Enclustra GmbH)
12:20 PM Conclusions: 1
1
12:20 PM - 1:00 PM
Room: 500/1-001 - Main Auditorium
Contributions

12:20 PM Summary of FDF26 and Awards - Rui Zou (Cornell University (US))

12:35 PM Closing Remarks - Francesco Gonnella (University of Birmingham (GB))
1:00 PM Lunch
Lunch
1:00 PM - 2:00 PM
Room: 500/1-001 - Main Auditorium
2:00 PM Tutorial: Better VHDL Test Reporting with OSVVM - Patrick Lehmann (PLC2)
Tutorial: Better VHDL Test Reporting with OSVVM (HDL verification and simulation tools)
- Patrick Lehmann (PLC2)
2:00 PM - 5:00 PM
Room: 6/R-012 - conference room According to Wilson Verification Survey, FPGA verification engineers spend 47% of their time debugging. This is no wonder as OSVVM's test suite produces log files that have 1.4M lines. Just sifting through the wealth of information and identifying the source of problems quickly is a challenge. To help, many approaches, including OSVVM, provide a JUnit XML based report (CI likes these) and a log file. OSVVM takes reporting further. OSVVM provides an HTML based build summary with VHDL test information (rather than Java) and includes links to details, such as test case reports, log files (HTML and text), requirement reports, and code coverage reports. OSVVM's test case reports contain detailed alert, functional coverage, and scoreboard statistics as well as links to the HTML log (jumping to this test case's results) and VHDL test case file (open in vscode or browser). With OSVVM, reporting is automatic and finding test information is just a click away.
Tutorial: DAQ Firmware Design with the colibri VHDL library - Alberto Perro (CERN) Mitja Vodnik (CERN)
Tutorial: DAQ Firmware Design with the colibri VHDL library
- Alberto Perro (CERN)
- Mitja Vodnik (CERN)
2:00 PM - 5:00 PM
Room: 2/R-030
Tutorial: HLS4ML - Georgios Flengas (CERN)
Tutorial: HLS4ML
- Georgios Flengas (CERN)
2:00 PM - 5:00 PM
Room: 13/2-005