3rd FPGA Developers' Forum (FDF) meeting

May 27, 2026, 9:00 AM → May 29, 2026, 8:00 PM Europe/Zurich

500/1-001 - Main Auditorium (CERN)

Davide Cieri (Max Planck Society (DE)), Francesco Gonnella (University of Birmingham (GB))

The FPGA Developers’ Forum (FDF) is a platform to discuss and exchange information, experiences, implementation ideas, tips, and tricks as well as challenges faced with design tools, specific FPGA technologies.

The 3rd FDF meeting will take place at CERN from 27th to 29th May 2026. We will discuss several FPGA related topics, look at the scientific programme on the sidebar for details.

We are open to new ideas and the list will be adapted depending on your contributions. Have you got something to share with the community?

Submit an abstract now for your presentation through the button below.

There is no registration fee, you’re very welcome to participate in the FDF meeting even if you’re not giving a talk. And remember that FDF is open to anyone, not only CERN users.

The FDF aims to form a topical community of digital designers, especially on FPGAs,  working in physics and beyond, and to discuss details that very rarely see the light of day in typical workshops in our field. 

We will focus on the ‘how’ digital designs are implemented rather than their scientific end-goal, and novelty is not the only criterion. Sharing tips on how to avoid pitfalls, or other ideas and recommendations that could save your colleagues precious time, are considered equally important.  

A CERN account is needed for the submission and registration. If you do not have one, it can be created here.

See you at CERN!

 

 

Wed, May 27

10:00 AM → 1:00 PM CERN Campus Visits: Visits

Convener: Filiberto Bonini (CERN)

1:00 PM → 2:00 PM Conference Registration: Participant Check-in

2:00 PM → 3:00 PM Introduction

Convener: Dr Francesco Gonnella (University of Birmingham (GB))

2:00 PM Welcome to FDF26

Speaker: Davide Cieri (Max Planck Society (DE))

Intro.pdf

Intro.pptx

Recording

2:10 PM What Star Trek can teach us about using AI in FPGA design

Like many engineers, I was initially sceptical of AI and its capabilities. However, over the last few years it has grown to be something FPGA engineers cannot ignore.

Can it help us as FPGA engineers do our jobs better, faster, smarter? In many ways, it’s the next natural layer of abstraction in FPGA design, extending a progression that has taken us from Boolean logic to schematics, HDLs to HLS. Its power lies in its ability to accelerate implementation, but it does not replace the engineer. Far from it.

In this session, we will look at how the effective use of AI calls for clear, structured guidance backed by deep technical knowledge. Taking Star Trek as an example, we have all seen Geordi La Forge or even Scottie talking to the computer to address engineering problems. They’re directing and guiding a capable assistant rather than presuming what the black box says is correct. Importantly, we must still understand what has been produced by AI, why it behaves as it does, and how to verify that it is accurate, secure, reliable, and safe. Used well, AI can increase productivity and help us meet shrinking schedules and expanding device capabilities. Used poorly, it can create confusion and technical debt.

The challenge is not whether to adopt AI, but how to equip the next generation with the expertise required to guide it, validate it, and ensure that it strengthens rather than weakens our engineering foundations in the future.

Speaker: Mr Adam Taylor (Adiuvo Engineering)

Recording

What Star Trek can teach us about using-final.pdf

What Star Trek can teach us about using-final.pdf

What Star Trek can teach us about using-final.pptx

3:00 PM → 3:45 PM Sponsor Presentations: Sponsor Presentaton

sponsor_talks.pdf

3:00 PM Altera

Speaker: Christian Faerber (Altera)

3:03 PM AMD

Speaker: Thilo Ohlemueller (AMD)

3:06 PM CAEN

Speaker: Luca Colombini (CAEN)

3:09 PM CAST

Speaker: Calliope-Louisa Sotiropoulou (CAST)

3:12 PM Efinix

Speaker: Mr Fabian Heinrici (Efinix)

3:15 PM iWave

Speaker: Sharath Kumar (iWave)

3:18 PM Knowledge Resources

Speaker: Bruno Monteiro (Knowledge Resources GmbH)

3:21 PM Lattice Semiconductor

Speaker: Hardik Shah (Lattice)

3:24 PM Microchip

Speaker: Mr Jens Huettemann (Microchip Technology Munich GmbH)

3:27 PM NanoXplore

Speaker: JEAN LOUIS FRIGOUL (NANOXPLORE)

3:30 PM PLC2

Speaker: Patrick Lehmann (PLC2)

3:33 PM ProDesign

Speaker: Stefan Rooseboom (ProDesign)

3:36 PM Samtec

Speakers: Neil Potter (Samtec), Veronique Branca (Samtec)

3:39 PM Techway

Speaker: Romain Larousse (Techway)

3:42 PM Trenz Electronic

Speaker: Martin Rohrmüller (Trenz Electronic)

3:45 PM → 4:15 PM Tea Break

4:15 PM → 6:30 PM Sharable HDL cores

Convener: Filiberto Bonini (CERN)

4:15 PM Scalable and lightweight RoCEv2 TX FPGA IP core

In many Data Acquisition (DAQ) systems, a significant portion of CPU resources is spent on networking rather than actual data processing. One way to reduce this overhead is to implement Remote Direct Memory Access (RDMA) directly in FPGA logic. Offloading RDMA to hardware can increase throughput, reduce latency, and significantly lower CPU utilization on the receiver side. This talk presents a scalable, portable, and lightweight RoCEv2 FPGA IP core. The architecture is intentionally simplified by removing the RX path and implementing only the TX side, specifically the SEND and RDMA WRITE operations, since FPGA-based DAQ applications typically do not require an RDMA receiver functionality. The IP has been validated at 10/25/100 Gbps on a Xilinx Virtex UltraScale+ FPGA (VCU118) and at 400 Gbps on a Xilinx Versal Premium ACAP (VPK180). We present measured throughput and Round-Trip Time (RTT) results, along with comparisons against NIC-to-NIC RDMA and standard TCP/IP solutions.

Speaker: Gabriele Bortolato (Universita e INFN, Padova (IT))

GB_MM_RoCEvfinal_FDF_2026.pdf

Recording

4:45 PM The PoC-Library - Free and Open-Source VHDL IP Core Library

The PoC-Library

The PoC-Library (Pile of Cores) is a free and open-source IP core library published since 2015 under Apache License, 2.0. It offers abstraction layers like the on-chip RAM modules (OCRAM) to abstract from device technologies, architectures and vendors. Therefor, the PoC-Library is independent from ASIC or FPGA, Altera or AMD/Xilinx devices or EDA toolchain.

Thís presentation will give an overview what the PoC-Library contains and how it will progress in future.

Selected topics

• Synchronizers
• RAM abstraction layer
• FIFOs
• AXI components
• Regression testing

Speaker: Patrick Lehmann (PLC2)

Recording

The PoC-Library 1 - Introduction.pptx

The-PoC-Library.pdf

5:25 PM NDK framework: Deep-Diving into High-Throughput Network Monitoring Pipelines

The Network Development Kit (NDK) is an open-source framework for high-speed FPGA network applications. Following up on last year’s overview and feature set, this presentation dives into the technical implementation and specific design challenges of building 400 GE network monitoring probes.
Monitoring probes perform wire-speed protocol parsing, traffic filtering, packet marking, and flow statistics calculation—tasks that overwhelm software-only solutions at high data rates. While HW offload is essential, implementing these functions at 400 Gbps in an FPGA is quite difficult. In the presentation, we will explain how we achieve this by processing multiple packets in each clock cycle, while delving into the pipeline of such a monitoring probe. Additionally, we will discuss the "causality" problem—where clock drift across different monitoring points causes network flows to appear out of order—and describe how we leverage White Rabbit synchronization to address it.

Speaker: Daniel Kondys (CESNET)

NDK on FDF2026.pdf

Recording

6:00 PM USB implementation with GateMate FPGA

GateMate FPGA from Cologne Chip [1] is natively supported by FOSS development tools (Yosys and nextpnr). The GateMate FPGA has a transceiver capable of communication at 5&nbsp Gbps. However, no open and free USB 3.x core is available for it. I'm running a project to implement a USB on the GateMate FPGA.

A hardware platform [2] (FPGA module and an adapter board) is designed, produced, and initially operated. An IP and firmware development is in the active phase.

The talk discusses the project scope, achieved results, and technical challenges. It is expected that by the time of the conference, a live demonstration will be possible.

The project is supported by the NLnet foundation [3].

[1] https://colognechip.com/programmable-logic/gatemate/
[2] https://www.gmm7550.dev/
[3] https://nlnet.nl/project/GateMate-USB3-PHY/

Speaker: Anton Kuzmin (gmm7550)

Recording

usb-implementation_2026-05-27.pdf

6:30 PM → 6:40 PM Group Photo

7:00 PM → 8:00 PM Poster Session and Welcome Reception: Posters are on display throughout the workshop. During the poster session, participants are free to browse at their own pace (no dedicated timeslot per poster; listed in Indico for reference only).

7:00 PM RoCE-Stream -- offloading (debug) data over 100Gbit RoCE RDMA

When developing FPGA applications, accessing real data can be a crucial help during debugging and algorithm development.
However, especially in applications with high data rates, it is often difficult to transfer data fast enough or buffer enough data.

This talk presents RoCE-Stream, an FPGA core, built upon the open-source fpga-network-stack, to transfer data from any AXI-Stream source to a PC over 100Gbit/s Ethernet. To achieve the data transfer rate, this core uses the RoCE protocol -- remote direct memory access (RDMA) over commodity ethernet.
By using RoCE, the receiving device can be any PC equipped with a 100Gbit network card.

Speaker: Alexander Daum (p2l2)

rfsoc_roce_offload_poster.pdf

7:01 PM CI-Driven FPGA ML Experimentation: Unified Results from HLS, Implementation, and On-Hardware Testing

This talk presents a CI-driven pipeline for FPGA machine-learning deployment optimized for rapid experimentation and reproducible comparison. The workflow automates ONNX/QONNX conversion, hls4ml project generation, build orchestration, and validation, allowing engineers to configure key design parameters directly from the CI interface for each experiment run. The main contribution is unified result collection across the full flow: HLS and implementation reports from Xilinx tools, model-quality checks, and on-hardware measurements from hardware-in-the-loop runs on ZCU102 (correctness, latency/throughput, and power trends). Instead of isolated tool outputs, every run produces comparable evidence in one place, enabling consistent trade-off analysis between accuracy, resources, and performance. The talk shares practical lessons from iterating on complex quantized models that are difficult to fit and turning FPGA deployment into a repeatable CI process.

Speaker: Georgios Flengas (CERN)

End-to-End CI-Driven FPGA ML Experimentation.pdf

7:02 PM XiBIF: A Python tool and hardware platform for streamlined FPGA development

XiBIF, short for Xilinx Board Interface, is an open-source FPGA development framework that combines a Python-based tool flow with a ready-made hardware platform featuring built-in communication over Ethernet.

The tool allows for quick project creation and ideation. It supports fast project setup, automated Vivado/Vitis build steps, and direct host-to-FPGA communication. Out-of-the-box, users can read and write custom memory-mapped registers, stream data, and reprogram the FPGA. XiBIF allows designers to focus on their ideas first, without the need for boilerplate code.

In this talk, we will introduce the XiBIF tool. We will explain the hardware platform and the ideas behind it, and demonstrate a complete workflow from project creation to hardware interaction.

Speakers: Mr Janik Witzig (Ostschweizer Fachhochschule), Lukas Leuenberger (Ostschweizer Fachhochschule)

XiBIF FDF Poster V9.pdf

7:03 PM Progressive Arithmetic Optimizations : Tensor and DSP Kernels to Synthesizable Datapaths

This work presents an end to end compilation flow that lowers high level machine learning and DSP kernels to explicit combinational and pipelined datapaths targeting FPGA and reconfigurable dataflow architectures. Arithmetic is treated as a multi level
concern, progressively exposing mathematical structure, numeric intent, and hardware organization from tensor programs to synthesizable RTL. The flow integrates real number expression recovery, configurable floating and fixed point realizations, and direct construction of structural datapaths. It leverages and extends FloPoCo by exposing its internal combinational graph as an intermediate representation, enabling operator based, fused, or specialized implementations such as Kulisch style accumulation. By keeping precision, approximation, and pipeline parameters explicit, the framework enables rapid Pareto exploration under joint accuracy, frequency, and FPGA resource constraints while preserving IEEE compliant floating point semantics.

Speaker: Louis Ledoux (INSA, INRIA)

7:04 PM Emulation of classic CPUs - a SoC-centric hybrid approach

The emulation of classic CPUs from the 1980s, such as the Motorola MC680xx series, is currently achieved through:

• (Full) software emulation running on a RISC processor
• (Full) hardware emulation (RT-level) on a programmable logic device (i.e. FPGA)

With the advent of SoC-FPGAs like the AMD Zynq, which combine CPU and FPGA logic in a single device, a platform is available for a hybrid approach to CPU emulation. This approach utilizes:

• The CPU of the SoC-device uses sequential code to replace large logic blocks in the hardware re-implementation.
• The FPGA part of the SoC uses programmable logic, the emulation of which would otherwise require many clock cycles.

Since this presentation is based on the author's personal work on reimplementing a 68k CPU in an AMD Zynq device, some practical anecdotes are also recounted, e.g.:
• Problems with mixed VHDL-Verilog
• Difficulties with memory interfaces intended to bypass the central data paths/bottlenecks of the Zynq architecture

Speaker: Volker Urban (Ingenieurbüro Dipl.-Ing. Volker Urban)

7:05 PM Benchmarking Neural Network Inference on Versal ACAP AI Engines for Real-Time Detector Alignment

Real-time detector alignment is critical for minimizing systematic biases in reconstructed trajectories. Standard calibration methods are often computationally expensive and struggle with latency in dynamic conditions. We propose a solution using a lightweight neural network with hierarchical subset solvers, optimized for the AMD Versal ACAP.

Our implementation maximizes heterogeneous efficiency by partitioning workloads: sequential tasks run on Scalar Engines (ARM CPUs), while compute-intensive matrix multiplications are offloaded to AI Engines (AIE) to leverage their vector processing capabilities.

We benchmark this AIE-accelerated design against traditional Programmable Logic (PL) and GPU implementations. We report on trade-offs involving latency, power density, and numerical precision. This work serves as a proof of concept for modern beam telescopes, demonstrating the viability of low-latency edge inference for future high-rate experiments.

Speaker: Haider Abidi (Brookhaven National Laboratory (US))

CERN-FDF-2026-amalige.pdf

7:06 PM Leveraging HBM for accelerating arbitrary Quantum Simulation on AMD Alveo platforms

Simulating quantum state vectors is constrained by the exponential scaling in computation complexity and data structure size, but well suited for parallel execution. However, existing methods struggle with fully leveraging DDR-based accelerators for the task. Furthermore, proposed FPGA designs lack "arbitrary operation" capability and scalability. This work introduces "labeled-random" state vector representation, aiming to combine the computational efficiency of sparse matrix multiplication with the parallelizability and sequential dataflow of conventional matrix multiplication. In addition, refining existing approaches led to replacing large operation matrices with lightweight bit-level operations, to enable scalable, parallel, arbitrary simulation. Our HBM-based prototype on an Alveo FPGA indicates a (scenario-dependent) factor 100 speedup potential over an HPC CPU node. The FPGA design facilitates future autonomous simulation, and adaptation to various usecase scenarios.

Speaker: Marwin Kirchhofs

poster_final.pdf

7:07 PM Towards a predictable toolchain dedicated to the generation of FPGA circuits for control algorithms

Aerospace systems are real-time critical, meaning they must meet strict timing and traceability constraints to avoid material damage and injuries. Systems present in particle accelerators may face the same constraints. FPGAs can be reconfigured and have the advantage that timing constraints can be easily guaranteed. Some HLS tools produce RTL code for configuring FPGAs from dataflow synchronous programming languages. However, the HLS process is often lengthy, may compromise the synchronous dataflow properties of the original programs, and lacks traceability.

To address this, researchers have explored the use of intermediate representations to compile programming languages into FPGA netlists. Building on this concept, we demonstrate how an intermediate representation can efficiently generate FPGA netlists from dataflow programming languages for the synthesis of control algorithms. We introduce a toolchain that provides a fast, predictable synthesis process with enhanced traceability.

Speaker: Inès Winandy (ENAC)

2026_FDF_Final (2).pdf

7:08 PM Qualifying FPGAs for Radiation-Tolerant Applications

Radiation effects are a critical concern for electronic systems operating in space, high-energy physics experiments, and other radiation-prone environments. Ensuring FPGA reliability in such conditions requires rigorous qualification methodologies to assess susceptibility to radiation-induced failures, including Single Event Latchup or Upset (SEL, SEU) and Total Ionizing Dose (TID) effects.

This talk presents the results of a comprehensive radiation qualification campaign conducted at CERN and a heavy-ion testing campaign at UCL to evaluate the radiation tolerance of GateMate FPGA devices. The session will provide an overview of the test methodologies used, including register tests, block RAM stability tests, and configuration memory robustness evaluations. These tests provide valuable insights into the FPGA’s ability to withstand radiation exposure while maintaining functional integrity.

Speaker: Patrick Urban (Cologne Chip AG)

fdf26-gatemate-poster.pdf

7:09 PM An Hardware Emulator for the ATLAS Phase-II L0MDT Trigger System

The L0MDT muon track finder algorithm will be implemented on the MDT Trigger Processor (MDTTP) ATCA board, featuring an AMD xcvu13p FPGA. To validate this, we propose using a 2020 demonstrator board (equipped with two AMD XCZU11EG FPGAs and three DDR4 modules) to emulate data flow.The demonstrator will simulate incoming signals from L0Muon systems (Front-End and Sector Logic) and internal MDTTP macroblocks. ATLAS Monte-Carlo or experimental data can be stored in the DDR4 memories and streamed at each clock cycle to mimic high-speed detector signals. This data is transferred via optical transceivers to the MDTTP board. As a primary use case, we present the validation of the transverse momentum ($p_T$) calculation block. We compare two approaches: a traditional empirical formula and a novel machine-learning algorithm implemented via hls4ml. This setup ensures the hardware can handle the rigorous demands of the ATLAS trigger system.

Speaker: Marcel Marques Boonen (Max Planck Society (DE))

ATL-DAQ-SLIDE-2026-210.pdf

7:10 PM Deep Memory for the Data Acquisition of the IceCube-Gen2 Surface Array

The IceCube Neutrino Observatory is a particle detector located at the South Pole, consisting of two components: a cubic-kilometer in-ice neutrino detector, and the IceTop surface array for high-energy cosmic rays.
For the proposed next generation neutrino observatory IceCube-Gen2, the surface instrumentation will be enhanced by an array of scintillators and radio antennas organized in local stations, where a scintillator coincidence or in-ice detection act as a trigger for the radio readout.
While this represents a common DAQ problem, the operational requirements and environmental constraints are special.
Available electrical power is limited, the DAQ must be able to operate at low temperatures, and the required radio buffer depth is high: 5 to 10 seconds at 800 MSa/s with 14-bit resolution.
This contribution presents a solution for long-term radio buffering based on LPDDR5 support of the upcoming AMD Spartan UltraScale+ FPGAs.

Speaker: Frederik Schmitt (Karlsruhe Institut of Technology)

IceCubeGen2_FDF2026.pdf

7:11 PM Practical Implementation of Lightweight Cryptography on FPGAs: Design Trade-offs, Side-Channel Considerations, and Integration Lessons

Lightweight cryptographic primitives are applied more and more in rugged FPGA systems with low resources where the security has to be weighed against the very strict limits of area, power, and latency. Even though the specifications have been around for a while, the efficient and secure hardware implementation is still a big challenge.

The above mentioned talk will tell about practical experiences of the application of lightweight cryptographic algorithms on FPGA devices with the comparison of serialized and partially unrolled architectures in terms of resource usage, throughput, and energy efficiency. The subjects of the talk will be constant-time design, side-channel leakage mitigation under very tight resource budgets and integration of lightweight cores into larger systems with standard buses. The common pitfalls of synthesis and placement-and-routing and the lessons learned will also be discussed in terms of long-term maintainability and portability.

Speaker: Pradeep Kumar Mohanty (NIT Rourkela)

7:12 PM POEMMA Balloon with Radio experiment as a use case for RFSoC in Astroparticle Physics

Radio Frequency System-on-Chip (RFSoC) is a powerful technology for various astroparticle physics experiments, in particular the ones using radio signals as the main detection channel. This poster will present the design of the RFSoC-based DAQ for the Radio Instrument of the POEMMA (Probe Of Extreme Multi-Messenger Astrophysics) Balloon with Radio (PBR) – a Super-Pressure Balloon experiment being prepared for launch from Wanaka, New Zealand. The main feature of the DAQ is the synchronized fast sampling of four individual RF signals coming from atmospheric particle cascades initiated by ultra-high-energy cosmic rays and detected by two dual-polarized antennas. The read-out is triggered both externally by a Cherenkov Camera and internally using a beam-forming technique. The collected experimental data can then be used for developing real-time denoising and classification machine learning algorithms which if implemented in RFSoC can significantly improve the self-trigger performance.

Speaker: Alexander Novikov (University of Delaware)

fdf26_Novikov_PBR_RI_DAQ .pdf

7:13 PM Transitioning to Modern FPGA Architectures in a High-Throughput Research Facility

Instruments at the European X-Ray Free Electron Laser (EuXFEL) receive femtosecond coherent X-ray pulses with 220 nanoseconds spacing in burst up to 3600 pulses every 100 ms.

As experimental demands increase, close interaction with users has led to the development of highly customized firmware and FPGA-based processing solutions. Leveraging our expertise, we plan to accelerate established data processing, reduction, and correlation software routines in hardware, enabling faster feedback and results. At the same time, the groundwork for in-house development of front-end electronics for next-generation 2D detectors is ongoing.

To sustain and scale this approach, we are transitioning to modern FPGA devices, updated toolflows, contemporary libraries, and open-source ecosystems. Our goal is to establish reproducible, maintainable workflows tightly integrated with control and IT infrastructure. We seek collaboration, guidance, and exchange of best practices from the FPGA community.

Speaker: Mr Bruno Fernandes (Eur.XFEL (European XFEL))

fdf2026_final.pdf

7:14 PM Geant4-driven realistic waveform generation for FPGA algorithm verification in radiation detector readout

FPGA firmware for radiation detector readout is often validated with idealized inputs that miss pile-up, baseline drift, statistical fluctuations and mixed fields. We present a simulation-driven workflow to generate realistic digitized waveforms using Geant4 and to reuse them for FPGA verification. Starting from energy deposition, we model detector response and electronics effects (shaping, noise, ADC quantization) and export time-aligned waveform and truth labels (hit time, energy, pile-up flags). The datasets are replayed into HDL/HLS testbenches and compared against a bit-accurate reference model to check latency, resource/precision trade-offs, and corner cases. We share practical lessons on dataset design, labeling, and regression testing that make firmware bring-up faster and more reliable.

Speaker: Ms Handan YILMAZ (istanbul technical University)

FDF2026_Poster_Handan_Yilmaz_ID75.pdf

7:15 PM Resource-Efficient Streaming Beam Reconstruction on an Intel Max 10 FPGA

The scintillating fiber and photodiode array–based beam profile monitor is being developed for the Heidelberg Ion Beam Therapy Centre as a next-generation device for ion beam therapy. The prototype acquires 320 channels of 16-bit data at a frame rate of 100µs on an Intel Max10 FPGA. The main challenge is to achieve fully hardware-based, low-latency beam reconstruction within the limited resources of Max10.
A resource-efficient streaming reconstruction architecture has been implemented, in which all channels are processed sequentially to minimize resource consumption. The chain includes pedestal subtraction, clustering, calibration, and moment calculation, and is implemented in fixed-point arithmetic with optimized bit widths. The design achieves a maximum latency of 27µs at 50 MHz, with excellent agreement with CPU-based results. This work forms part of the author's PhD research and is currently being further developed at HIT.

Speaker: Liqing Qin (Heidelberg Ion Beam Therapy Centre)

7:16 PM JEDI-linear: Fast and Efficient Graph Neural Networks for Jet Tagging on FPGAs

Graph Neural Networks (GNNs), especially Interaction Networks, achieve strong jet tagging performance at the CERN HL-LHC but are difficult to deploy on FPGAs due to high complexity and irregular memory access under strict latency constraints. We propose JEDI-linear, a GNN with linear complexity that removes explicit pairwise interactions using shared transformations and global aggregation. We further apply fine-grained quantization-aware training with per-parameter bitwidth optimization and multiplier-free distributed arithmetic. On FPGA, JEDI-linear achieves 3.7–11.5× lower latency, up to 150× lower initiation interval, and up to 6.2× lower LUT usage than prior GNNs, while improving accuracy and removing DSP usage. It is the first interaction-based GNN below 60 ns latency, meeting HL-LHC CMS Level-1 trigger requirements, and is released open-source to support reproducible, real-time scientific ML.

Speaker: Zhiqiang Que (University of Bristol)

jedilinear_fdf_165.pdf

7:17 PM Reconciling Fixed-Frequency Clocking and Variable Sampling-Rate Data: Real-Time Arbitrary Resampling for Stream Processing

We present an IP core for arbitrary and real-time variable sampling rate conversion in data-stream processing. The IP solves a common design challenge in CERN synchrotrons: maintaining a fixed ADC/FPGA system clock (White Rabbit based), preferred for timing closure and clock-domain robustness, while processing data at a rate proportional to the beam revolution frequency, the so-called bunch synchronous clock.
Based on Farrow fractional delay filters, the IP decouples sampling and system clocks-domains. It enables static logic, predictable latency under a fixed hardware clock and stable feedback systems.
Implemented in System Generator and deployed in the CERN SPS LLRF system, demonstrating performance and robustness in operational accelerators, it solves the transfer of data between clock-domains with unrelated sampling rates. The IP and methodology are reusable for any system requiring synchronization to a varying reference and can be extended to implement real-time feedback loops.

Speaker: Javier Galindo Guarch (Aragon Institute of Technology Itainnova (ES))

FDF2026_Poster_JG.pdf

7:18 PM Low-Complexity Median Algorithm in FPGA for AMS-02 Layer-0 Upgrade

The Streaming Median Algorithm (SMA) implements an heap-sorting algorithm to compute median in FPGA exploiting its concurrent architecture. SMA consists of 2 heaps: max-heap sorts the lower values while min-heap the upper values. Each new 16-bit word is inserted in either of the 2 roots, and a rebalancing follows each insertion. Eventually, root of max-heap represents the maximum of the lower values and the root of min-heap the minimum of the higher values. The median is the average of the 2 roots. We designed SMA for the AMS-02 Layer-0 upgrade, to compute the common noise (CN) that affects all of the 64 channels of a front-end ASIC (FE). Since the FE streams the 16-bit ADC values, SMA can rebalance the heaps before the next word is available and immediately provide the median. Exploiting the median of medians principle, we kept complexity low while meeting throughput specifications, also by optimizing the basic cells of the heaps for concurrent rebalance.

Speaker: Luca Russo (Universita e INFN, Perugia (IT))

2026 FDF Poster Russo

7:19 PM AI Inference in FPGAs for both Standard and Safe & Dependable Applications

We present a solution for AI inference on heterogeneous AI accelerators with some acceleration microkernels implemented in an FPGA. The solution is part of a software framework for AI execution orchestration that can be optimised for latency & power on constrained embedded systems. This orchestration can trigger AI execution on a diversity of AI accelerators, for example GPUs but also NEON/DSP SIMD accelerators, external rad hardened co-processors like the HPDP and, crucially, FPGAs.
We detail the orchestration environment and the design decisions behind the FPGA microkernel interface, the current microkernel designs to date and the performance characteristics. We pay particular attention to the questions of scalability and co-existence with other FPGA IP. We end by describing the V&V environment and the development process for new FPGA microkernels - for for instance dependable AI execution.

Speaker: David Ganz (ZHAW)

FDF26-Poster-InES_HIS-ganz.pdf

7:20 PM SVN is better than GIT for FPGA development: I will die on this hill

We discuss and contrast SVN vs. GIT for FPGA HDL development. Hierarchical designs with multiple repositories are common for large FPGA projects. SVN:Externals provides native hierarchical support with precise submodule references, requiring no plugins or scripting. GIT Submodules are cumbersome by contrast and require careful cross-repository coordination. More critically, GIT clones entire repository histories locally, a big problem for hierarchical designs. For example, a 3-level, 4-submodule per level hierarchy yields 21 full repository checkouts. FPGA binary files such as bitstreams and build artifacts inflate repositories with every commit, but should be version-controlled since routine recompilation is not efficient given that FPGA builds often take hours or days. We discuss GIT shallow cloning and GIT-LFS and show that these provide inferior solutions to SVN. Though not the conventional wisdom, we contend that SVN is demonstrably superior to GIT for FPGA HDL development.

Speaker: Yair Linn (TRIUMF)

SVN_vs_GIT_FDF26_Poster_final2.pdf

7:21 PM Using native libraries functions from VHDL with VHPIDIRECT

VHPIDIRECT is a simple API originally implemented in GHDL and later adopted by NVC that allows VHDL functions and procedures to be implemented in any language that compiles into native code and exposes a C ABI calling convention. As an example of its capabilities, this work presents a VHDL package that has been developed to write an HDF5 file containing frame data decoded from Timepix4 raw packets collected from a real device.

Speaker: Augusto Fraga Giachero (CNPEM / LNLS)

7:22 PM MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks

Deep neural networks (DNNs) have been applied across diverse domains, including safety-critical applications. Past studies indicate that DNNs are very sensitive to changes in weights and activations due to uneven bit-weight distribution in standard number formats like fixed points, which can cause significant output accuracy fluctuations. To address this issue, we introduce a new data type called MONO to enhance bit flip resilience using uniformity at the bit level by employing symmetric weights for all bit positions. On average, MONO has improved error resilience more effectively than the fixed-point data type, even when utilizing triple modular redundancy (TMR) and most significant bit (MSB) protection, while maintaining low overhead.

Speaker: Maryam Eslami (Ruhr-Universität Bochum)

MONO_CERN.pdf

7:23 PM PandA-Bambu Backend for hls4ml

Portable, reproducible FPGA ML inference benefits from open-source, vendor-agnostic HLS flows. We present a new hls4ml backend for PandA-Bambu, an open-source HLS tool that generates RTL from C/C++. The backend adds Bambu-specific writer integration, Bambu-compatible datatypes, and pragma/code-generation support for synthesis and simulation, together with template/numerical variants (e.g., compile-time activations) and backend-oriented updates for Dense and Convolution layers. Bambu broadens target support for hls4ml beyond Vitis-centric toolchains, enabling paths toward NanoXplore platforms. To assess QoR, we align build/report pipelines and compare Bambu vs. Vitis using resource utilization, power, and latency, progressing from layer tests to end-to-end network evaluation to quantify functional equivalence, trade-offs, and backend maturity.

Speaker: Nicolo Ghielmetti (CERN)

nicologhielmetti_poster_fdf.pdf

7:24 PM From C/C++ to Hardware with Bambu: An Open-Source HLS Research Tool

This talk presents Bambu, an open-source research and development platform for high-level synthesis (HLS). Bambu (https://github.com/ferrandi/PandA-bambu) supports rapid experimentation across high-level verification and debugging, FPGA/ASIC design, design-flow space exploration, and parallel accelerator generation. It supports standard C/C++, enabling the EDA community to prototype new transformations and optimizations. Its modular architecture bundles optimizations and HLS benchmarks for systematic quality-of-results (QoR) assessment, and connects to commercial and open-source synthesis/verification backends to quickly obtain performance and resource metrics. Bambu targets multiple FPGA families (AMD/Xilinx, Intel/Altera, Lattice, NanoXplore). We are extending Bambu’s interfaces and integrating with HLS4ML for ultra-low-latency FPGA inference.

Speaker: Mr Tommaso Fellegara (Politecnico di Milano)

BambuPoster.pdf

7:25 PM ARTEMIS: FPGA-based AD in the ATLAS Level-1 Trigger

The LHC can provide up to 40 MHz of proton-proton collisions to the ATLAS experiment, which must be filtered in real time down to 100 kHz in order to meet the readout constraints. This task is performed by the Level-1 Trigger, which uses FPGA-based hardware to select the most relevant events within a few microseconds. Traditionally, Level-1 Trigger algorithms have been designed to target a set of predefined, interesting Physics signatures. In recent years, anomaly detection (AD) triggers have also been explored, aiming to flag events that deviate from the expected behaviour and to increase the sensitivity to rare or unforeseen phenomena. ARTEMIS is the latest AD trigger implemented in ATLAS. This poster discusses the architecture of its neural-network and the key differences with respect to previous approaches, as well as some of the challenges faced when implementing it in hardware.

Speaker: Paula Martinez Suarez (CERN)

PMS_FDF_2026.pdf

7:26 PM Implementation of Elias deterministic extractor for true random number generation

This work presents an FPGA-based implementation of the Elias algorithm for deterministic entropy extraction. The input consists of strongly biased binary sequences generated by a single-photon detector, forming a true Quantum Random Number Generator (QRNG). Assuming the raw bits are independent and identically distributed with unknown bias, the Elias extractor deterministically converts this sequence into a shorter stream of provably unbiased and independent bits, without requiring additional randomness. Such extractors are fundamental for reliably extracting truly random bits from physical sources. We discuss architectural considerations for efficient mapping onto reconfigurable logic and analyse trade-offs in throughput, latency, and resource utilization, demonstrating practical high-speed quantum randomness conditioning in hardware.

Speaker: Lorenzo Borella (Universita e INFN, Padova (IT))

Borella_poster_FDF.pdf

7:27 PM The Firmware Development Kit (FDK)

The Firmware Development Kit (FDK) is a software application that simplifies HDL version management, build tool project creation, and build flow management for FPGA. The software is used by staff in the Technology Department at STFC and is now being commercialised. The FDK provides the following functionality:

• Simplified build tool project creation. The FDK parser reads the HDL to determine which files should be added to a project.
• Automatic creation of Sigasi projects in VS Code.
• Automatic version numbering and change log generation.
• Automatic documentation generation.
• Simplified development of continuous integration tests. The CLI simplifies the development of scripted build flows.
• Simplified sharing of projects. A single command can be used to recreate a project.
• Automatic generation of VHDL register descriptions and interconnects from XML specifications. The same XML description can be used to create memory mapped resources that comply with different bus standards.

Speaker: Adam Lee Barcock (Science and Technology Facilities Council STFC (GB))

260518_fdk_poster_a0_portrait.pdf

7:28 PM Frame Buffering Design Strategies for Boosting Mobipix 15D X-Ray Imaging Rates

Closing timing constraints becomes increasingly challenging as FPGA solutions grow in area utilization. This work presents a frame-rate enhancement technique using FPGA frame buffering for SIRIUS Mobipix 15D, a Medipix3RX-based area detector, generating larger composite images for transmission over a camera serial interface to a System-on-Module (SoM), thereby increasing the effective X-ray acquisition rate while maintaining a protocol-level frame rate compatible with conventional cameras.

The implementation required >95% Block RAM utilization, spreading the design across nearly the entire FPGA and creating significant timing closure challenges at 200 MHz. Beyond conventional pipelining for high-fanout paths, an iterative approach was applied by repeating post-placement optimization, noticeably improving timing closure capability. These strategies increased frame-buffering capacity from 2x to 6x without violations, raising the detector’s safe operating rate from 200 fps to 1200 fps.

Speaker: Mr Allan Borgato (LNLS)

Allan_Borgato_FDF_2026_poster.pdf

Thu, May 28

9:00 AM → 10:30 AM Verification: 1

Convener: Mathieu Saccani (CERN)

9:00 AM Inside UVVM: Architecture and Design of Custom Verification Components

This talk takes an in-depth look inside a UVVM VVC, explaining its internal architecture and core design principles. Key concepts such as the command-based interface, command queue, command interpreter, and executor are explored in detail, along with synchronization mechanisms, transaction handling, and the interaction with Bus Functional Models (BFMs).

Building on this foundation, the presentation demonstrates how to develop custom UVVM-compliant VVCs using the official templates and generator support. Practical guidance and best practices are shared to help attendees design reusable, maintainable, and well-integrated verification components that fit seamlessly into existing UVVM-based testbenches.

The talk is aimed at FPGA developers who are already familiar with the basics of UVVM and want to move beyond using existing VVCs—gaining the confidence to understand, extend, and create their own verification components.

Speaker: Markus Leiter (p2l2)

Markus_Leiter_Inside_UVVM.pdf

Recording

9:30 AM Open-source simulation landscape and advances towards mixed language support

The current scenario of HDL open-source simulators has changed significantly, raising the question of what cases traditional commercial simulators are still necessary.

GHDL and NVC are advancing quickly towards full VHDL 2008 compliance in addition to experimental VHDL 2019 support in NVC. Mixed language simulation has been a challenge with open-source tools, previous attempts used language translation to convert Verilog to VHDL and vice versa. Recently, NVC has added experimental support to Verilog, opening the path to true mixed language simulation with open-source tools. This presentation intends to show the capabilities of open-source simulators, compare these with commercial solutions and discuss the current challenges with open-source tools.

Speaker: Augusto Fraga Giachero (CNPEM / LNLS)

os-simulation-landscape.pdf

Recording

10:00 AM Open Source HDL Co-Simulation with AMD Alveo

HDL simulation is essential for verifying digital designs, but its computational intensity often results in slow turnaround times, delaying development cycles.
This presentation demonstrates how AMD Alveo FPGA acceleration cards, integrated with open source HDL simulators and frameworks, can dramatically speed up simulation workflows.

The presentation begins by outlining the bottlenecks in traditional HDL simulation and the potential of FPGA-based acceleration.
Next, I present the methodology, focusing on the integration of Alveo cards with open source tools, and share practical insights into setup, optimization, and common pitfalls.
Finally, I showcase performance benchmarks and real-world use cases, outlining additional benefits of using co-simulation besides the expected performance increase.

Speaker: Matthias Kern (p2l2)

OpenSourceHDLCoSimulation.pdf

OpenSourceHDLCoSimulation.pptx

Recording

10:30 AM → 11:00 AM Coffee break

11:00 AM → 12:35 PM AI: 1

Convener: Dr Rui Zou (Cornell University (US))

11:00 AM AMD Embedded AI Solutions

AI-driven applications in industrial automation, robotics, automotive, and scientific instrumentation demand high inference performance with low, predictable latency and long-term reliability. These demands can only be met by local AI processing for which AMD offers complementary embedded AI platforms.

The Ryzen AI Embedded processor family integrates CPU, GPU, and NPU compute engines on a single SoC, supporting CNNs, vision transformers, SLMs, and LLMs via mature open source software stacks.

The Versal AI Edge Gen 2 Adaptive SoC combines high-performance scalar cores, a dedicated neural engine, and programmable logic to deliver single-chip end-to-end pipelines spanning sensor fusion, perception, analytics, and HMI.

Demonstrated applications include 120 FPS object detection with YOLOv8m on Versal AI Edge Gen 2 and real-time optical flow inference on the Ryzen AI iGPU using PyTorch + ROCm at 30 FPS.

AMD's unique combination of CPU, GPU, NPU, and programmable logic, backed by mature open-source software stacks, enables intelligence at the edge with low and predictable latency, scalable throughput, and functional safety.

Speaker: Mr Thomas Gmeinder (AMD)

AMD Embedded AI Overview CERN.pdf

Recording

11:45 AM KalEdge-Lite: Hardware-Aware ML-to-FPGA Deployment with Automated hls4ml Integration

KalEdge-Lite is a hardware-aware framework that automates neural network deployment on FPGA platforms through an end-to-end ML-to-bitstream workflow. The system integrates model training, compression techniques, hardware-aware evaluation, and automated accelerator generation. A regime-aware analytical model estimates FPGA resource utilization and latency before synthesis, enabling rapid identification of hardware-feasible configurations without repeated HLS execution. KalEdge-Lite supports multiple FPGA platforms and enables reproducible deployment from trained models to validated hardware implementations. The presentation will demonstrate practical deployment workflows and discuss experience using automated hardware-aware configuration screening for FPGA-based neural network acceleration.

Speaker: Romina Soledad Molina (kaleidoforge)

kaledge_presentation.html

Recording

12:05 PM HGQ: High Granularity Quantization for Real-time Neural Networks and LUT-Based Inference

Neural networks with sub-microsecond inference latency are required by many critical applications.
Targeting such applications deployed on FPGAs, we present High Granularity Quantization (HGQ), a quantization-aware training framework that optimizes parameter bit-widths through gradient descent.
Unlike conventional methods, HGQ determines the optimal bit-width for each parameter independently, making it suitable for hardware supporting heterogeneous, arbitrary precision arithmetic.
Simultaneously, we introduce HGQ-LUT, a new class of LUT-based layers implemented within HGQ with regular tensor operations during training
, enabling the efficient optimization of LUT-based or hybrid neural networks with more than 2 orders of magnitude faster training speed compared to previous methods.
We show that the HGQ framework achieves superior performance compared to previous arts, achieving significant reduction in resource consumption and latency while maintaining the accuracy.

Speaker: Chang Sun (California Institute of Technology (US))

hgq.pdf

Recording

12:35 PM → 1:35 PM Lunch

1:35 PM → 4:05 PM Algorithm Implementation: 1

Conveners: N. Engelhardt (YosysHQ), Tom Williams (Rutherford Appleton Laboratory (GB))

1:35 PM NGRC on SoC for online learning of dynamical systems

Predicting the evolution and control of dynamic systems in real time remains a demanding task for conventional methods that depend on accurate models and intensive continuous optimization, which often breaks under uncertainty, noise or delays. Reservoir Computing (RC) provides a lightweight alternative, needing only small training sets and simple inference. We present a low‑cost, low‑power platform that couples next‑generation RC (NGRC) with continuous online learning to forecast long horizons of the Lorenz attractor. The system runs on a Zynq‑7000 SoC: the FPGA accelerates reservoir inference loop, while the ARM CPU manages data acquisition, weight updates and control. With naïve implementation a latency of 148.5 ms on CPU side + 1.5 ms on FPGA is achieved. Results demonstrate that NGRC on modest SoC hardware can deliver energy‑efficient, real‑time predictions of chaotic systems, enabling edge deployment in autonomous vehicles, robotics, satellites and high‑energy physics.

Speaker: João Folhadela (German Aerospace Center)

NGRC on SoC for online learning of dynamical.pptx

Recording

2:05 PM Accelerating Data: Lossless Compression for HPC, Datacenter, AI, and Scientific Data Pipelines

High-performance computing and data-intensive infrastructures are increasingly limited by data movement rather than processing power. Large scientific experiments such as those at CERN, together with AI training clusters and datacenters, generate continuous data streams that must be handled at multi-100 Gb/s under strict latency, power, and storage constraints. Lossless compression in FPGA or ASIC hardware reduces bandwidth and memory needs without altering scientific results, precision, or training accuracy.
This presentation examines hardware architectures for lossless compression in HPC, AI, datacenter, and scientific data acquisition systems. Emphasis is on deterministic-latency pipelines operating inline with Ethernet, PCIe, high-bandwidth memory, and storage. Algorithms including LZ4, Snappy, GZIP/DEFLATE/Zlib, and Zstandard are compared in terms of ratio, resource cost, and throughput, highlighting the trade-off between ultra-low-latency cores and higher-ratio formats.

Speaker: Calliope-Louisa Sotiropoulou (CAST)

Accelerating_Data_Lossless_Compression_FPGA_AI_HPC_v3.pdf

Recording

2:35 PM High-speed digital twins: Pushing simulation time-steps into the nanosecond range using Versal ACAP

In the design and validation of high-speed electrical systems, such as power converters, the fidelity of the electrical model is strictly limited by the minimum achievable time-step. Conventional FPGA-based simulators often operate in the range of microseconds or, at best, several hundred nanoseconds. This limitation can lead to failures in capturing high-speed transients or introduce numerical instabilities caused by the solver constraints.

This presentation explores how combining discretized mathematical models with AMD Versal can be leveraged to push real-time simulations down into the nanosecond range. We will first discuss the creation of high-efficiency RTL models for power converters and their conversion into synthesizable block diagrams. Finally, we will demonstrate how by using the Versal architecture, we can enable the execution of these models at high-speeds, even allowing us to offload part of the instrumentation and measurement logic directly into the FPGA design.

Speaker: Pablo Trujillo (controlpaths)

Pushing simulation time-steps into the nanosecond range using VERSAL ACAP r1b.pdf

Recording

3:05 PM Study of non linearities on the AMD Phase Interpolator

In the context of high precision timing distribution there is a growing awareness of phase instabilities. Novel solutions are relying on phase tracking and phase shifting to stabilize clocks and data streams.
AMD transceivers provide an ultra fine phase shifter (phase interpolator), with a step smaller than 2 ps, which can be controlled by the user to phase shift the transmitted data.
This device presents non linearities which worsen the accuracy of the nominal step size, up to an error of 3 ps.
This research presents a characterization of the non linearity of the phase interpolator, describing its variability over temperature, firmware recompilations and different transceivers.
It is shown how to consider the characteristic of non linearity to improve a phase compensation algorithm. The shift steps can be chosen based on the knowledge of the error distribution over the range of the phase interpolator, to improve its accuracy.

Speaker: Edoardo Orzes (CERN)

FDF2026-txpi-use.pdf

Recording

3:35 PM Dynamic Derandomizing Buffer: A Portable and Scalable Solution for Time-Ordered Packet Aggregation

The Dynamic Derandomizing Buffer is a firmware design for joining time-stamped packets form multiple incoming data streams with randomly varying time-skews into a single time-ordered output stream. It is developed at CERN primarily to handle the output from the novel FastRICH ASIC (the LHCb RICH detector readout chip for Runs 4 and 5), but intentionally made agnostic to this use-case so it can be used in any similar real-time stream processing scenario. Written in pure VHDL, it is also fully portable: it was successfully built for both Intel and AMD devices.

This presentation covers a scalable and configurable tree-based aggregation architecture, portable BRAM-based buffering components, and a special time-stamp windowing algorithm which guides the time-ordering process. We also share our experience in applying test-driven development approach (using formal verification and self-testing UVVM-based simulation) to a complex FPGA design.

Speaker: Mitja Vodnik (CERN)

FDF26 DDB.pdf

Recording

4:05 PM → 4:35 PM Tea Break

4:35 PM → 6:30 PM HDL Development Tools: 1

Convener: Dr Nicolo Vladi Biesuz (Universita e INFN, Ferrara (IT))

4:35 PM Tools and libraries Review

FDF supports a number of free OS tools and libraries useful to the FPGA community.

This talk will give you the chance to meet the tools' authors!

FDF Tools

Speaker: Francesco Gonnella (University of Birmingham (GB))

FDF26-tools.pdf

FDF26-tools.pptx

Recording

5:05 PM VHDL-LS - A Free and Open Source Language Server for VHDL

VHDL-LS is one of the most popular free and open-source Language Servers for VHDL as measured by GitHub stars. With features such as syntax and type checking, code navigation, completion and many more, it boosts developers abilities to write VHDL code.

This talk dives deeper into the basics of language servers, presents the current state of VHDL-LS and demonstrates its capabilities such as semantic analysis, diagnostics, code navigation and editor integration. We will discuss how these features improve productivity and code quality for FPGA developers. Finally, we outline future ambitions for VHDL-LS, including the development of a language API and a broader ecosystem of VHDL tooling wit the aim of modernizing VHDL development, enabling new forms of automation and analysis.

Speaker: Lukas Scheller (KIT)

FDF26 VHDL-LS.pdf

FDF26 VHDL-LS.pptx

Recording

5:40 PM fwk: An Open-Source Framework for Standardized FPGA Development at DESY

At DESY, the increasing complexity of control systems for particle accelerators requires a standardized approach to FPGA development. We present fwk, an open-source framework designed to abstract design logic from underlying vendor-specific implementation tools. The framework provides a unified environment for managing IP cores, project generation, and register mapping across different hardware platforms. Complementing this infrastructure, DESY is actively releasing a growing library of VHDL IP cores to the public, underscoring an institutional commitment to open-source instrumentation. Additionally, fwk addresses the integration of heterogeneous processing units by coordinating the build processes for embedded runtime environments, such as Yocto and FreeRTOS. The presentation outlines the framework’s design principles and provides an overview of its application in current accelerator subsystems.

Speaker: Cagil Gumus (DESY)

Presentation.pdf

Recording

6:00 PM DevOps for FPGA 101: from version control to hardware-in-the-loop testing

This talk demonstrates that adopting DevOps principles for FPGA projects is neither complex nor prohibitively expensive. Using widely available open-source tools, mature software-style pipelines can be applied to hardware design with meaningful productivity gains.

The presentation will cover a practical end-to-end approach, including:
- Effective use of Git-based version control for HDL, constraints, IP cores, and testbenches
- Automated CI pipelines for synthesis, place-and-route, and bitstream generation
- Testing via simulation
- Hardware-in-the-loop (HIL) validation using FPGA boards with CI runners
- Automated firmware loading, test execution, and result reporting for closed-loop verification

The talk concludes with a concrete industrial case study: the ASIC prototyping phase of an edge AI audio processing device.

Speaker: Matteo Vit (Starware Design)

MatteoVit_StarwareDesign_DevOps101.pdf

Recording

7:15 PM → 10:35 PM Social Dinner

Fri, May 29

9:00 AM → 10:10 AM Solutions to everyday digital design problems: 1

Convener: Dr Paschalis Vichoudis (CERN)

9:00 AM The CERN Open Hardware Licence for FPGA Designs

Version 2 of the CERN Open Hardware Licence was published in 2020 and approved by OSI in 2021. During its drafting, a great deal of thought and discussions were devoted to catering for the specificities of IC and FPGA design. The licence comes in three variants in order to give these communities appropriate tools for sharing in the three usual regimes: permissive (P), weakly-reciprocal (W) and strongly-reciprocal (S). The talk will cover the basics of licensing, differences between software, hardware and documentation licensing and practicalities such as how to use each of the licence variants in FPGA designs. The CERN OHL v2 was a community effort with many designers and legal experts involved. The presentation will also discuss the importance of open-sourcing, the new Open Source Program Office (OSPO) at CERN and how it can help FPGA designers share their work efficiently.

Speaker: Javier Serrano (CERN)

js_fdf_2026_05_29.pdf

Recording

9:25 AM Kyokko2: a portable multi-gigabit serial communication controller

This work proposes a synchronous version of Kyokko, a vendor-independent serial communication IP. Kyokko is our open-source implementation of Aurora 64B/66B and separates the device-independent protocol layer from the device-specific transceiver interface, enabling portability across multiple FPGA vendors. The original Kyokko design requires a 64:66 asynchronous gearbox on the FPGA's transceiver. However, as data rates increase, most recent FPGA transceivers omit asynchronous gearboxes, limiting the portability of the Kyokko. To address this, we redesign Kyokko for synchronous gearboxes that operate their PCS and PMA at the same clock frequency. The proposed architecture improves compatibility with recent transceivers from Altrera, AMD, Lattice, and other vendors. This work enables vendor-mixed FPGA-based instrumentation systems and computing environments.

Speaker: Sou Tanaka (Osana Lab)

Recording

sou_kyokko2.pdf

sou_kyokko2_pp.pptx

9:45 AM A Multigigabit Link Layer Protocol for Single Picosecond Latency Determinism Using AMD Ultrascale+ GTH and GTY Transceivers

Precision timing distribution systems require deterministic and repeatable high speed serial data link latency. The EIC Timing Data Link will employ a specialized link layer protocol for deterministic multigigabit communication using AMD Ultrascale+ GTH and GTY transceivers. Link latency must also be measurable to accurately compensate in real time for latency variations of the physical medium. The point-to-point link is full duplex and fully synchronous with a latency control algorithm to align the internal clocks of each system with picosecond resolution. Deterministic clock domain crossing between systems is ensured using static timing analysis of the elastic buffer control signals.

Speaker: Paul Bachek (Brookhaven National Lab)

latency deterministic link.pdf

latency deterministic link.pptx

Recording

10:10 AM → 10:40 AM Coffee break

10:40 AM → 12:20 PM Solutions to everyday digital design problems: 2

Convener: Evangelia Gousiou (CERN)

10:40 AM Latency analysis of the CPU-FPGA interface in the Zynq UltraScale+ SoC

Real-time control algorithms for power converters in particle accelerators require flexible platforms capable of high iteration rates (up to 100 kHz).
This work evaluates the suitability of the Zynq UltraScale+ SoC (A53 cores) for such applications. After characterizing the access time of the most basic FPGA-CPU access path, we show how this path is unsuitable for real time controls. We then propose an alternative system, characterizing the critical metrics: PL access, Memory access, ACP latency performance, and Interrupt latency. We identify a suitable data path for real time controls and propose an exploitation paradigm for achieving reliable sub-microsecond latency.

Speaker: Valerio Nappi (CERN)

Recording

vnappi-fdf-26.pdf

vnappi-fdf-26.pptx

11:05 AM Recovered Clock Phase Monitoring on AMD Transceivers for Deterministic Timing

After the Phase-II upgrade of the Large Hadron Collider at CERN, pile-up discrimination in the CMS Electromagnetic Barrel Calorimeter demands a clock system with picosecond precision and deterministic phase. Although modern electronics can achieve sub-5 ps RMS jitter, widely used FPGAs do not ensure phase repeatability after reset. Their Multi-Gigabit Transceivers prioritize bit error rate robustness over deterministic recovered clock phase. Measurements with the Barrel Calorimeter Processor (BCP-V2) show that MGT resets can yield two discrete recovered clock phases about 10 ps apart, while the internal Delay Aligner adds temperature-dependent drift. The BCP-V2 integrates a picosecond-resolution monitor achitecture that extracts the clock before the Delay Aligner and the FPGA fabric (RXRECCLKOUT) and compares it to RXUSRCLK, typically used as the LHC reference, using a Digital Dual Mixer Time Difference method, enabling real-time detection of clock phase jumps and drifts.

Speaker: Nikitas Loukas (University of Notre Dame (US))

2026_05_29_nloukas_FDF.pdf

Recording

11:30 AM SystemVerilog Hacks: Circumventing the Limitations of SystemVerilog

SystemVerilog is a powerful language with relatively good compiler support. However, some inexplicable oversights and limitations in the SystemVerilog standard can cause HDL designers to expend significant work that would have been unnecessary had simple tweaks in the language's standard been adopted. For example, one limitation of SystemVerilog is that a "struct" cannot be parameterized more than once, i.e. the same "struct" code needs to be rewritten every time any of the parameters that define it change. A similar issue affects SystemVerilog functions. With regards to SystemVerilog interfaces, a necessary but lacking feature of SystemVerilog would be the ability to propagate parameters directly from an interface to other parts of the code, without needing to pass the parameters themselves up and down the design hierarchy. In this presentation we discuss these and other issues and their workaround solutions that enable the designer to make much more efficient use of SystemVerilog.

Speaker: Yair Linn (TRIUMF)

Recording

SystemVerilog_Hacks.pdf

11:50 AM CDCs, FIFOs, and Width Converters: How to Combine Open Logic Building Blocks Correctly

In FPGA design, correctly handling clock domain crossings, buffering data streams, and matching data widths is critical for reliable and maintainable systems. The Open Logic FPGA Standard Library (open source) provides building blocks for these challenges, but many users struggle to understand when and how to combine them effectively.

This talk will walk you through the CDCs, FIFOs, and width converters in Open Logic and provide clear guidance on selecting and composing them for different scenarios, including asymmetric buffering and varying bandwidth requirements. Attendees will leave with actionable rules and patterns to use Open Logic building blocks correctly, avoid common pitfalls, and simplify FPGA system design.

Speaker: Oliver Bründler (Enclustra GmbH)

OpenLogic.pdf

OpenLogic.pdf

OpenLogic.pptx

Recording

12:20 PM → 1:00 PM Conclusions: 1

Convener: Davide Cieri (Max Planck Society (DE))

fdf-vote.pdf

12:20 PM Summary of FDF26 and Awards

Speaker: Dr Rui Zou (Cornell University (US))

FDF26_Summary_Awards_RZou.pdf

12:35 PM Closing Remarks

Speaker: Francesco Gonnella (University of Birmingham (GB))

outtro2026.pdf

outtro2026.pptx

Recording

1:00 PM → 2:00 PM Lunch

2:00 PM → 5:00 PM Tutorial: Better VHDL Test Reporting with OSVVM

According to Wilson Verification Survey, FPGA verification engineers spend 47% of their time debugging. This is no wonder as OSVVM's test suite produces log files that have 1.4M lines. Just sifting through the wealth of information and identifying the source of problems quickly is a challenge.

To help, many approaches, including OSVVM, provide a JUnit XML based report (CI likes these) and a log file.

OSVVM takes reporting further. OSVVM provides an HTML based build summary with VHDL test information (rather than Java) and includes links to details, such as test case reports, log files (HTML and text), requirement reports, and code coverage reports. OSVVM's test case reports contain detailed alert, functional coverage, and scoreboard statistics as well as links to the HTML log (jumping to this test case's results) and VHDL test case file (open in vscode or browser).

With OSVVM, reporting is automatic and finding test information is just a click away.

Speaker: Mr Patrick Lehmann (PLC2)

Agenda

2:00 PM → 5:00 PM Tutorial: DAQ Firmware Design with the colibri VHDL library

Speakers: Alberto Perro (CERN), Mitja Vodnik (CERN)

colibri_tutorial_fdf26.pdf

Prerequisites and materials

ZOOM Recording

2:00 PM → 5:00 PM Tutorial: HLS4ML

Speaker: Georgios Flengas (CERN)

Agenda

FDF-hls4ml .pdf