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Description
This work presents a comparative study and optimization of a fast charge-sensitive amplifier (CSA) intended for hybrid pixel detectors operating in single-photon-counting (SPC) mode. The design objective is to minimize electronic noise while maximizing pulse-processing speed under stringent power constraints. Two advanced technology nodes are investigated: a 40 nm planar CMOS process and a 16 nm FinFET technology.
The CSA serves as the front-end stage of the readout chain and is optimized for low input capacitance typical of pixel detectors (~50 fF) and ultra-low power operation, with a bias current of approximately 5 µA. The core amplifier is designed to operate in the weak inversion (subthreshold) regime to maximize transconductance efficiency and achieve low-noise performance within limited power budgets. Particular emphasis is placed on the noise–speed trade-off and on the implementation of compensation techniques that ensure stable operation and fast pulse shaping across process variations and detector conditions.
Comprehensive simulations and performance analyses demonstrate that the FinFET-based implementation provides a significant improvement in pulse-processing speed compared to the planar CMOS counterpart, primarily due to superior electrostatic control and increased intrinsic device gain. Importantly, low-noise performance is preserved despite aggressive device scaling. These results highlight the strong potential of FinFET technology for next-generation high-rate photon-counting detectors, where both timing resolution and energy accuracy must be maintained under strict power constraints.
This work is supported by the National Science Centre, Poland, project no. 2023/51/B/ST7/01782.