Speaker
Description
SHINE (Shanghai HIgh repetitioN rate XFEL and Extreme light facility) is the first XFEL facility working in the hard X-ray region in China. To fulfill the special requirements of SHINE, a new pixel array detector, STARLIGHT (SemiconducTor Array detectoR with Large dynamIc ranGe and cHarge integrating readout), is being developed. HYLITE (High dYnamic range free electron Laser Imaging deTEctor)) is the front-end readout chip of STARLIGHT, which works in the charge-integration mode with a dynamic range of 1~10000 photons @ 12 keV. To enable such high speed, a 10-bit Analog-to-Digital Converter (ADC) is integrated into each pixel, ensuring that the pixel outputs are in digital format.
The HYLITE series is manufactured using a 130 nm CMOS process. The initial phase of HYLITE, HYLITE200F, was developed focusing on creating a 64×64-pixel chip with a 200-μm pixel pitch. The maximum frame rate of the first full-scale chip is 6.3 kHz in successive readout mode. The performances of the HYLITE200F chip are fully tested. The signal-to-noise ratio is 8.7, which indicates the ability for single-photon resolution. The 2×8-size front-end module has been manufactured to organize a single-module prototype detector system and has been adopted successfully on the SAXS end station of HEPS. Imaging tests show that the function of the module and the architecture of the detector are correct.
HYLITE100F is the second engineering run chip of HYLITE, aiming for a frame rate of 10 kHz. Compared with HYLITE200F, the pixel pitch of HYLITE100F is improved from 200 μm to 100 μm, while the maximum data rate is increased from 400 Mbps to 3.28 Gbps. The array size of the full-size chip is 128×128. In this architecture, two data ports are used for whole-chip data transmission. Each data port consists of a high-speed serializer, a low-speed serializer, and a CML (Current Mode Logic) driver. A clock management block was also integrated into the periphery of HYLITE100F to generate the necessary clocks, which consist of a PLL (Phase Lock Loop) and a frequency divider. The tests were carried out on a 16-ASIC test module without the sensor. An eye diagram analysis confirmed that the data port operates effectively at a data rate of 2 Gbps. The primary imaging tests showed that the function of the ASIC is correct. In this poster, we will introduce the design and test progress of the HYLITE series chips.