Participating: Ilias, Eric, Tomas, Dominik.

Carboard v1.5 validation (Ilias):

• Debugging the 4 boards with issues at CERN
  • One from old batch with soldering issues at FMC connectors --> to be sent back to Safiral for repair
  • One with open between connectors for DP2 high-speed-link line (X-ray of connectors looks fine, traces inside board cannot be followed in Xray). --> to be checked with Safiral how to proceed.
  • One with CMOS line 9 issue. Was seen on other boards for same line. Seems a design flaw (though not confirmed). Line not much used in current designs (except for one Xray application at DESY) --> Will add a sticker on the board with this information and keep it at CERN.
  • One with I2C issue (no clock visible on one I2C line). --> Tomas suggests some further debugging to be done by Ilias. 
• SPARC chipboard status (Tomas)
  • Components have still not arrived at DESY. Many people on holiday this week. --> to be followed up early next week.
  • Plan to populate all 25 boards at once. Send one without chip to Vienna for DAQ tests, and possibly same for some other lab(s). 
  • DD has 15x "split 4" SPARCs and 5x "split 6" SPARCs at CERN that can be used for the Caribou chipboards. --> chipboards to be sent to CERN as soon as they are available.
• Use cases / tests of the Carboard testing suite developed by Ilias and Abraham
  •  It would be good to try the test setup at DESY, on the boards that are currently at DESY. This would validate the completeness of the documentation of the test setup, and also validate the boards at DESY (increasing the validation statistics). It can also be a good exercise for a new person to become familiar with Caribou while doing something useful at the same time. 
  • Tomas has Electronics Engineering Master Student, who is interested in project on SoC for his Master. He will try to use the DMA implementation on work on it further. He could also initially use the testing setup to become familiar with Caribou. Will only be available from summer. 
• Carboard v2 design (Eric)
  • Slow progress, busy with other projects.
  • Plan is still that Eric does the schematics, while the layout will be done by the design service at BNL.