PiPPo

<h1>PiPPo</h1>
<ul>
<li><code>issue_422</code> still have some timing errors in the lpGBT core (I think it might require some pipeline to relax timing, to be checked if this would break the code</li>
</ul>
<p> </p>
<p> </p>
<pre>-1.303    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_lpgbtfpga_uplink|frame_pipelined_s[18]    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_lpgbtfpga_uplink|lpgbtfpga_decoder_inst|fec12_correction_pattern_o[167]    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_alt_a10_gx_320mhz_latopt_x1|xcvr_native_a10_0|rx_clkout    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_alt_a10_gx_320mhz_latopt_x1|xcvr_native_a10_0|rx_clkout    3.150    -0.057    4.560    Slow 900mV 100C Model<br>-1.303    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_lpgbtfpga_uplink|frame_pipelined_s[18]    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_lpgbtfpga_uplink|lpgbtfpga_decoder_inst|fec12_correction_pattern_o[162]    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_alt_a10_gx_320mhz_latopt_x1|xcvr_native_a10_0|rx_clkout    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_alt_a10_gx_320mhz_latopt_x1|xcvr_native_a10_0|rx_clkout    3.132    -0.057    4.618    Slow 900mV 100C Model<br>-1.303    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_lpgbtfpga_uplink|frame_pipelined_s[18]    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_lpgbtfpga_uplink|lpgbtfpga_decoder_inst|fec12_correction_pattern_o[158]    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_alt_a10_gx_320mhz_latopt_x1|xcvr_native_a10_0|rx_clkout    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_alt_a10_gx_320mhz_latopt_x1|xcvr_native_a10_0|rx_clkout    3.125    -0.057    4.536    Slow 900mV 100C Model<br>-1.302    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_lpgbtfpga_uplink|frame_pipelined_s[134]    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_lpgbtfpga_uplink|lpgbtfpga_decoder_inst|fec12_correction_pattern_o[162]    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_alt_a10_gx_320mhz_latopt_x1|xcvr_native_a10_0|rx_clkout    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_alt_a10_gx_320mhz_latopt_x1|xcvr_native_a10_0|rx_clkout    3.132    -0.041    4.633    Slow 900mV 100C Model<br>-1.302    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_lpgbtfpga_uplink|frame_pipelined_s[134]    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_lpgbtfpga_uplink|lpgbtfpga_decoder_inst|fec12_correction_pattern_o[158]    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_alt_a10_gx_320mhz_latopt_x1|xcvr_native_a10_0|rx_clkout    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_alt_a10_gx_320mhz_latopt_x1|xcvr_native_a10_0|rx_clkout    3.125    -0.041    4.551    Slow 900mV 100C Model<br>-1.302    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_lpgbtfpga_uplink|frame_pipelined_s[134]    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_lpgbtfpga_uplink|lpgbtfpga_decoder_inst|fec12_correction_pattern_o[167]    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_alt_a10_gx_320mhz_latopt_x1|xcvr_native_a10_0|rx_clkout    corecmp|cmp_gbt_wrapper|g_gbt_bank[3].cmp_lpgbt_bank|g_gbt_link[4].cmp_lpgbt_link|cmp_alt_a10_gx_320mhz_latopt_x1|xcvr_native_a10_0|rx_clkout    3.150    -0.041    4.575    Slow 900mV 100C Model</pre>
<p> </p>
<ul>
<li>compiling the production firmware with the new QUARTUS (required by TPC). I have some large timing errors, I think I am missing some constraints between 2 clocks ... following this</li>
<li>I got some connector to properly plug the vtrx+ and the fiber ... will repeat the test with the long fibers once attached.</li>
</ul>