FPGA SoCs: Unleashing the Next Generation of Embedded Systems

by Dr Andrea Stanco (University of Padova)

Tuesday 21 Jul 2026, 14:00 → Wednesday 22 Jul 2026, 16:00 Europe/Zurich

593/R-010 - Salle 11 (CERN)

Abstract

his module deals with the design of FPGA+CPU embedded systems, where Programmable Logic and a Processor coexist on the same chip — the so-called System-on-a-Chip (SoC) — built around the AMD-Xilinx Zynq-7000 family. After introducing the architecture of the Processor–Logic interface — the AXI interconnect, memory-mapped access to peripherals, and interrupt handling — the course follows the full design flow: the hardware platform is defined in Vivado using Block Design and IP integration, then exported to Vitis, where the bare-metal application, able to interact with the FPGA hardware, is developed. The course also addresses how the processor and the programmable logic can exchange data, the deployment of the system on the board, the communication between the system and the external world, and hardware/software debugging. The final goal is to gain a first complete view of a working embedded system that might be deployed in a real-world scenario. The module is meant to give participants a practical understanding of how such systems are put together and how to approach the full system design. It is divided between lectures and guided hands-on lab activities on Zynq-7000 development boards.

Lecturer Biography

Andrea Stanco was born in Padua, Italy. He received the M.Sc. degree in electronic engineering and the Ph.D. degree in information engineering from the University of Padova, Padua, in 2014 and 2019, respectively.
He is currently a Research Fellow at the Department of Information Engineering, University of Padova, where he conducts research on digital electronic systems for quantum applications. His research interests include FPGA architectures, embedded systems, and electronics for satellite quantum communications.