With Moore's Law alive and well, more and more parallelism is introduced into all computing platforms at all levels of integration and programming to achieve higher performance and energy efficiency. Especially in the area of High-Performance Computing (HPC) users can entertain a combination of different hardware and software parallel architectures and programming environments. Those technologies range from vectorization and SIMD computation over shared memory multi-threading (e.g. OpenMP) to distributed memory message passing (e.g. MPI) on cluster systems. We will discuss HPC industry trends and Intel's approach to it from processor/system architectures and research activities to hardware and software tools technologies. This includes the recently announced new Intel(r) Many Integrated Core (MIC) architecture for highly-parallel workloads and general purpose, energy efficient TFLOPS performance, some of its architectural features and its programming environment. At the end we will have a brief look at Exa-Scale computing, its challenges and opportunities.
Dr. Herbert Cornelius is WW HPC Solution Architect at Intel with focus on technical, high-performance computing (HPC) and many-core computing. Before he was Engineering Manager in Intel's Cluster Software & Technologies group in EMEA, working on scalable parallel computing hardware & software solutions based on vectorization, multi-threading and message-passing utilizing multi-core/multi-processor cluster platforms. Before joining Intel, he served as Manager High-End Computing Europe at Fujitsu and worked at Cray Research from 1983 to 1990. He received a Ph.D. degree in Mathematics and Diploma degree in Mathematics and Informatics from Technical University of Berlin, Germany.
Organised by: Sverre Jarp and Miguel Angel Marquina
Computing Seminars /IT Department