EP-ESE Electronics Seminars

Designing HEP circuits in 65nm

Name: Designing HEP circuits in 65nm
Start: 2012-06-05T09:00:00+02:00
End: 2012-06-05T10:00:00+02:00
Location: CERN

by Pierpaolo Valerio (Universita e INFN, Roma I (IT)), Dr Sandro Bonacini (CERN)

Tuesday 5 Jun 2012, 09:00 → 10:00 Europe/Zurich

13/2-005 (CERN)