Clock distribution

• Stéphane and Jakov are working on individual components and exploring different architectures.
• This is currently the only part of the LLRF consolidation for which resources are granted, at least in terms of manpower. Hardware funding still needs to be clarified (rough estimate: 50–100 kCHF).
• Measurements of the phase stability at different locations have already been performed and reported.
  • Stéphane Rey to share the corresponding report.
• A layout of the present clock distribution was prepared by Stéphane Curt in 2024 (available on Indico).
• Stéphane and Jakov need the requirements for the clock distribution ASAP. In particular, we need to identify which users/applications require which level of clock stability, at which frequencies, and at which locations.
  • Expected requirements from possible future FCC-related users/applications should also be included.
  • Recent laser requirements should be checked carefully, as they may go beyond what was documented by Stéphane in 2024.
  • Requirements from the new LLRF system (see below) should also be fulfilled 
• Typical parameters to specify include:
  • Location (rack / building / destination) where the clock is required.
  • Phase noise / stability / reproducibility within the ~5 us RF pulse.
  • Pulse-to-pulse phase stability.
  • Amplitude stability (within the 5us RF pulse, and pulse-to-pulse).

We agreed to start by defining the required stability at the high-power structure level, and then work together with the RF colleagues to translate this backwards into requirements along the RF/clock chain. The schematics already prepared by Stéphane Curt provide a good starting point.

Tentative timeline: agree on all specifications by the end of 2026, with progressive implementation potentially starting from mid-2027 and completion during YETS 2027/28.

Fast delay units

• Today’s ECL counters have a set resolution of 4 ps.
• An SY-RF solution providing 10 ps resolution and 1 ps stability should be available. Details can be checked with Ben Woolley.
• A crate implementing this solution is already used in AWAKE.
• TTL-to-ECL and ECL-to-TTL converter cards are available as part of this solution and, if needed, could be deployed in one of the VME crates next to our existing ECL counters.

From an after-meeting discussion with Ben, it appears that this could provide a quick backup solution in case of problems with our present TTL/ECL converter cards, which are currently one of the most critical items as we have no spares.

LLRF klystron drive and signal acquisition / infrastructure

• The new LLRF system based on uTCA cards follows the baseline developed for AWAKE.
  • Some prototype hardware should in principle be available.
  • No FESA class is currently available.
  • For the FESA class, or more generally the interface with users/operations, the experience of BE-OP colleagues could be very valuable.
• In principle, this system could also be deployed for CLEAR and/or future FCC-related tests in CTF3.
  • There are currently no concrete plans to deploy it in CLEAR.
  • Minimum requirements nevertheless need to be defined.
  • In particular, a diagram of all LLRF acquisitions should be prepared, including signals and acquisition locations. This is especially important because several signals are currently digitised remotely in building 2010, while the original LLRF is located in building 2001.
• The proposed new LLRF stations require only the 3 GHz reference and 125 MHz for synchronisation.
• Acquisition cards for this system can digitise up to 7 I/Q signals per card, removing the need for some external phase shifters, e.g. for the comparator phase as done today.
  • Each system can host up to 6 cards (one card may be required for the klystron drive, where applicable.)
  • The cards are designed to operate around 3 GHz. It is not yet clear whether they can also operate at 1.5 GHz.
    • It should therefore be assumed for the moment that the laser 1.5 GHz phase shifter will remain in place.

There is currently no concrete deployment plan for this system. Nevertheless, the requirements should be defined by the end of 2026, with first inputs needed ASAP.

Interlock and safety chain

• The present LLRF PLCs are used to control the phase shifters and final-stage LLRF amplifiers. This also includes functions related to the safety-chain interlocks.
• The new LLRF system could potentially integrate safety-chain interlock capabilities, but this needs to be studied and verified.
• For the moment, the assumption is that the existing PLC network must remain in place.
• If the new LLRF system is eventually deployed, it will need either to replace these functions or interface appropriately with the existing PLC/interlock system (but this should be avoided, if possible).

RF signal acquisition chain

• The present system is based on signals digitised in OASIS and subsequently processed in XenericSampler.
• The proposal is to ask the BE-OP colleagues supporting us during LS3 to:
  • investigate how to port the present data-treatment code from XenericSampler towards a new solution (e.g. UCAP);
  • verify that the present hardware acquisition chain provides all the required signals and identify any missing acquisitions.
• In the longer term, if the new LLRF system is deployed, two possible approaches could be considered:
  1. Provide the acquired data in place of OASIS to XenericSampler, or to its future equivalent.
  2. Have the new LLRF system directly provide calibrated amplitude and phase information.

Actions

• Stéphane Rey: share the report on the phase-stability measurements performed at the different locations.
• CLEAR team: collect and consolidate clock-distribution requirements from all users/applications.
• Edu / LASER team: check recent present and future requirements for clocks
• Steffen / RF team: include potential future FCC-related requirements in the clock-distribution specifications.
• CLEAR team (with help of RF team): define required stability at the high-power structure level and translate it into requirements along the RF/clock chain.
• CLEAR team: prepare a diagram of all present/required LLRF signals, acquisitions and locations (buildings 2001/2010).
• LLRF team: clarify whether the new acquisition cards can operate at 1.5 GHz in addition to 3 GHz.
• LLRF team: study how the new LLRF could interface with or eventually replace the existing PLC/interlock functions.
• BE-OP / CLEAR: investigate during LS3 a replacement for the present OASIS/XenericSampler processing chain (e.g. UCAP) and check for missing acquisitions.
• Stéphane: prepare a rough estimate of the required LLRF consolidation budget for 2026 and 2027.
• All: aim to finalise the main LLRF/clock requirements by end of 2026.