11-15 February 2013
Vienna University of Technology
Europe/Vienna timezone

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

14 Feb 2013, 16:30
20m
EI7 (Vienna University of Technology)

EI7

Vienna University of Technology

Speaker

Dr Gianluca Traversi (University of Bergamo)

Description

This work presents the characterization of Deep N-Well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130nm CMOS process where the top tier is thinned down to about 12um to expose the through silicon vias (TSV), therefore making connection to the buried circuit possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization activity on the SDR1 chip and on different kind of test structures, including single pixels, 3x3, 8x8 and 16x16 matrices will be presented at the conference.
quote your primary experiment ILC

Primary author

Dr Gianluca Traversi (University of Bergamo)

Co-authors

Alessia Manazza (Università degli Studi di Pavia) Lodovico Ratti (University of Pavia) Luigi Gaioni (Universita e INFN (IT)) Massimo Manghisoni (Università di Bergamo - Italy) Valerio Re (INFN)

Presentation Materials