14-18 October 2013
Amsterdam, Beurs van Berlage
Europe/Amsterdam timezone

Beyond core count: a look at new mainstream computing platforms for HEP workloads

15 Oct 2013, 14:30
Veilingzaal (Amsterdam, Beurs van Berlage)


Amsterdam, Beurs van Berlage

Oral presentation to parallel session Facilities, Production Infrastructures, Networking and Collaborative Tools Facilities, Infrastructures, Networking and Collaborative Tools


Pawel Szostek (CERN)


As Moore’s Law continues to deliver more and more transistors, the mainstream processor industry is preparing to expand its investments in areas other than simple core count. These new interests include deep integration of on-chip components, advanced vector units, memory, cache and interconnect technologies. We examine these moving trends with parallelized and vectorized High Energy Physics workloads in mind. In particular, we report on practical experience resulting from experiments with scalable HEP benchmarks on the Intel “Ivy Bridge-EP” and “Haswell” processor families. In addition, we examine the benefits of the new “Haswell” microarchitecture and its impact on multiple facets of HEP software. Finally, we report on the power efficiency of new systems.

Primary authors

Presentation Materials