14-18 October 2013
Amsterdam, Beurs van Berlage
Europe/Amsterdam timezone

The core trigger software framework of the ATLAS experiment

15 Oct 2013, 16:05
Verwey Kamer (Amsterdam, Beurs van Berlage)

Verwey Kamer

Amsterdam, Beurs van Berlage

Oral presentation to parallel session Data acquisition, trigger and controls Data Acquisition, Trigger and Controls


Tomasz Bold (AGH Univ. of Science and Technology, Krakow)


The high level trigger (HLT) of the ATLAS experiment at the LHC selects interesting proton-proton and heavy ion collision events for the wide ranging ATLAS physics program. The HLT examines events selected by the level-1 hardware trigger using a combination of specially designed software algorithms and offline reconstruction algorithms. The flexible design of the entire trigger system was critical for the success of the ATLAS data taking during the first run of the LHC. The flexibility of the HLT is due to a versatile core software which includes a steering infrastructure, responsible for configuration and execution of hundreds of trigger algorithms, and navigation infrastructure, responsible for storing trigger results for physics analysis and combining algorithms into multi-object triggers. The multi-object triggers are crucial for efficient selection of interesting physics events at high LHC luminosity while running within limited bandwidth budgets. A resource consumption by the software algorithms was minimized thanks to a sophisticated navigation interface which encapsulates trigger logic and caches results of trigger algorithms. Detailed description of the steering and navigation infrastructures will be presented together with details of the caching implementation and results of operating the system with and without the caching. In preparation for future LHC running conditions, a new software interface has been developed to maximize benefit from new commodity computing hardware for CPU intensive parts of the HLT. The interface contains a software layer which provides hardware abstraction and handles the data communication between the existing software components and the optimized algorithms that are executed on the dedicated computing resource. This layer is extensible and suitable for multi-threaded, multi-process, multi-node environment utilizing diverse hardware resources. The results of the tests on various hardware platforms and with several programming systems will be presented.

Primary authors

Dmitry Emeliyanov (STFC - Science & Technology Facilities Council (GB)) Rustem Ospanov (University of Pennsylvania) Dr Sami Kama (Southern Methodist University (US))

Presentation Materials