Speaker
Wim Lavrijsen
(Lawrence Berkeley National Lab. (US))
Description
Intel recently released the first commercial boards of its Many Integrated Core (MIC) Architecture. MIC is Intel's solution for the domain of throughput computing, currently dominated by general purpose programming on graphics processors (GPGPU). MIC allows the use of the more familiar x86 programming model and supports standard technologies such as OpenMP, MPI, and Intel's Threading Building Blocks. This should make it possible to develop for both throughput and latency devices using a single code base. In ATLAS Software, track reconstruction has been shown to be a good candidate for throughput computing on GPGPU devices. In addition, the newly proposed offline parallel event-processing framework, GaudiHive, uses TBB for task scheduling. The MIC is thus, in principle, a good fit for this domain. In this presentation, we report our experiences of porting to and optimizing ATLAS tracking algorithms for the MIC, comparing the programmability and relative cost/performance of the MIC against those of current GPGPUs and latency-optimized CPUs.
Primary author
Wim Lavrijsen
(Lawrence Berkeley National Lab. (US))
Co-authors
Manuel Neumann
(Bergische Universitaet Wuppertal (DE))
Roberto Agostino Vitillo
(Lawrence Berkeley National Lab. (US))
Dr
Sami Kama
(Southern Methodist University (US))
Sebastian Fleischmann
(Bergische Universitaet Wuppertal (DE))
