There is now a well established baseline design for the future CMS Tracker to be used after 2025 at the HL-LHC. The upgrade requires complete replacement of the present tracker with a higher granularity detector which must contribute information to the Level 1 trigger. The working design contains a pixel detector at small radii and an outer tracker (30cm< r <120cm and end-caps) instrumented as two regions. The outermost region (60cm < r < 120cm, and outer end-cap disks) will be populated by so-called 2S-PT modules with two closely spaced microstrip sensor layers, providing L1 triggering information by correlating hits in the two layers to reject low transverse momentum track hits, and reduce the L1 data volume. The 2S designation refers to the two microstrip-sensor layers. A similar approach is adopted for the inner region of the outer tracker with increased segmentation in z, where one of the sensor layers is coarsely pixelated, hence known as PS modules.
A novel, highly flexible processing architecture for the calorimeter trigger has been adopted by CMS for the Phase I upgrade. In a traditional trigger system, each module processes data from a small part of the detector using pipelined logic. Seamless coverage of the detector requires many cross-links between modules, and the dataflow architecture is fixed in the system design, for instance by the routing on crate backplanes. In the Time-Multiplexed Trigger (TMT), the system instead transfers all data corresponding to a given bunch-crossing into a single hardware module, with many identical modules working in parallel on different bunch-crossings. This approach is similar to that used by the CMS event builder.
The new calorimeter TMT trigger is designed with two layers. The first transfers data rapidly to the Layer 2 processing nodes where trigger algorithms run, but the system can be constructed with identical boards in both layers with advantages for maintenance, operation and overall cost. The current µTCA FPGA processor board is called the MP7, based on a Xilinx Virtex-7 FPGA and Avago MiniPOD optics, which provides a powerful flexible processor core with 72 input and 72 output serial optical links, all running at 10 Gbps. The new system has been successfully demonstrated in a series of tests and will be commissioned in CMS during 2015 data taking, in parallel with the existing trigger, so that it can be deployed during 2016 operations.
The TMT architecture can be deployed in a future tracking system. A conceptual design for such a system, based on MP7s, has been devised which allows to estimate the requirements to build such a system. The first layer of MP7s would perform the function of the Front End Drivers in the present CMS silicon tracker but also transmit the tracker data to a second layer of MP7s which would carry out the track finding which is envisaged to take place in the Layer 2 FPGAs. One reason to investigate this approach is to establish whether this method of track finding can be proven to work with an acceptable efficiency and latency, which must be a few µs.
Progress with the TMT in the Phase I calorimeter trigger will be summarised. The Phase II track-trigger system design will be explained including the motivations for the parameters adopted. A demonstrator system can be constructed using available hardware and is planned to take place during 2014. The plans to do this will be described.