Comments from Herve:

I remind that Orsay plans to design and built the FE boards, Cagliari and Saclay would be involved on the data transmission part (e-links, GBT boards…).
Saclay can also help in  the expertise on FEE.


I see already some points to discuss (others will certainly come during the discussion):
1) First proto type (3 channels)
- description: will it involves analogic + digital + part of DSP ?
- what kind of outputs are foreseen ? .. at which levels ?
- how to control the chip : kind of slow control ?

- which tests are foreseen by the brazilian team ?
- these tests would be performed a test bench developed by the brazilian team ? 

=>  These tests are at the SAMPA level

       2) First proto (3 channels) 
 =>  tests at FE card level ??:  this point is not so clear if we can do test at the FE card level , 
- so develop a FE card with proto 3 channels ? 
- and which  tests ? … : 
- test on test bench would not give much more information than at the SAMPA level ?
- test on detector ? …. to look at noise ? but not in environment …
- test on detector in beam tests ???   …. 

3) Test bench for future FE card with 32 channels prototype
- Orsay is planning to design a test bench to test the specifications of the 32 channels SAMPA on a FE card
- It will require informations from the SAMPA layout and pinout : these informations will probably come only in fall 2014 ?

3) Come back on SAMPA specifications
- try to understand the impact of the 9.2 effective ADC bit
  - DNL/INL noise ?    and the relation to ENOB
- ENOB: is it related to non-linearities ? …. and can we correct them ?

- pedestal, zero suppression; pedestal subtraction: how is it done ?
                       - there is a baseline correction at the analog level : I suppose it is to rectify the baseline
                       - there is also a baseline correction at the digital level (even 2 corrections ?): is it for pedestal subtraction ?

    ……


These are some of the questions we could discuss next week.


Comments from Ketil:

* We need to discuss how and which types of irradiation test we would like to perform

* Cumulative effects:

* TID: We expect a rather low dose, < 10kRad, so TID is not of significant concern. Nevertheless, it should be tested to confirm a higher tolerance. Can potentially be done in combination with SEE testing using a proton beam.
* Displacement damage: Again rather low total fluence values, and CMOS devices are in general not very sensitive to DD. 

* Single Event Effects

* Single Event Latchup, SEL: One should plan to do some type of SEL testing. That is, one should be able to measure the current consumption of the device and register any high current events.  A latchup protection and detection mechanism is therefore needed in the test setup. Could be on a circuit level or maybe also a current limited power supply that can automatically be power cycle on high current events. 


* Our environment consist mainly of high energy hadrons  (HEH) where the secondary fragments from nuclear interactions in the device material can induce high charge deposition events and thereby SEL. This SEL sensitivity of the device will therefore depend on the material composition of the device. E.g. if the device used tungsten plugs, fission reactions in tungsten can induce high LET fragments. 
* Have TSMC or CERN already done any SEL testing of the relevant 130 nm process?
* Do we know or can we learn anything about the materials which are used in our process? Can we e.g. find out if tungsten is used? TSMC will probably not disclose this information but we should consider if a reverse engineering approach should be taken to investigate the material composition. 
* As we operate in a HEH environment we should discuss if it is needed to test the device with heavy ions or not.


* We could test the device at a standard test facility providing 230 MeV protons like e.g. PSI, and then at the new mixed facility CHARM at CERN were the environment also will consist of particles with higher energies. This should cover the range of particle in  the ALICE TPC environment.

* Single event transients, SET: Discuss which parts of the design that could be sensitive to SET:
  ADC?
  Digital parts?
  How can this be tested?

* Single event upsets (SEU): Discuss which parts of the design that could be sensitive to SEU.
  Will we be able to monitor any of the digital parts in the design?
  Would we be able to measure the SEU cross section of any of the memory elements in the SAMPA chip.
  Do the ADC have any memory elements that could be sensitive to SEUs, or latch SETs?

* In general, does CERN have available test methodology (test board designs) for SEL, SEU etc testing of their prototypes, and can we in any way benefit from this?
* Design mitigation
  As far as I understand CERN is currently working on implementing the 65 nm process for TSMC where they would like         to  build radiation hardened libraries. (http://indico.cern.ch/getFile.py/access?contribId=243&sessionId=20&resId=5&materialId=slides&confId=228972 [1])  

*

* It seems like they would like to do the same with 130 nm process, and also investigate the radiation hardness of this process,  but they are probably at the moment prioritising the work on the 65 nm process. We should investigate if we possible could participate in this process and contribute to the porting of the libraries to the 130 nm process. 
* This could be of interest to us as we could then maybe use some of the radiation hardened cells as building blocks for the SAMPA chip. It could also be interesting to see if we could collaborate on the irradiation testing. 
* I believe they also have done some work on an ADC for 65 nm (possibly even radiation hardened), can we use or port this design without to much effort to 130 nm?


* What are the specification of this ADC. I think for example that it has a lower sampling rate of 1MS/s compared to our requirement of 10MS/s. 
* Can we possible apply some of the mitigation approaches to the SAMPA ADC in the 130 nm process (Could this be a task that you could be involved in).