Sep 22 – 26, 2014
Centre des Congrès - Aix en Provence, France
Europe/Zurich timezone

Global Trigger Upgrade Firmware Architecture for the Level-1 Trigger of the CMS Experiment

Sep 23, 2014, 5:15 PM
1m
Centre des Congrès - Aix en Provence, France

Centre des Congrès - Aix en Provence, France

14 boulevard Carnot 13100
Poster Trigger First Poster Session

Speaker

Dr Babak Rahbaran (Austrian Academy of Sciences (AT))

Description

The Global Trigger (GT) is the final step of the CMS Level-1 Trigger and implements the “menu'' of triggers, which is a set of selection requirements applied to the final list of objects (such as muons, electrons or jets) to trigger the readout of the detector and serve as basis for further calculations by the High Level Trigger. Operational experience in developing trigger menus from the first LHC run has shown that the requirements increased as the luminosity and pile-up increased. The new GT is designed based on Xilinx Virtex-7 FPGAs, which combine unsurpassed flexibility with regard to scalability and high robustness.

Summary

The Global Trigger (GT) is the final step of the Level-l Trigger of the CMS (Compact Muon Solenoid) experiment at CERN. The upgraded system is based on uTCA technology and 10GBps optical links. It implements the “menu'” of triggers, which is a set of selection requirements applied to the final list of objects (i.e. electrons/photons, muons, jets, taus, etc.), required by the algorithms of the High Level Trigger to meet the physics data-taking objectives. This menu will include triggers ranging from simple single object selections with Et above a set threshold to selections requiring coincidences of several objects with topological conditions amongst them. Trigger conditions will be defined by using the “L1-Trigger Menu Editor (L1TME)” software. This software interface facilitates reprogramming the FPGA logic by translating human-readable physics algorithms into the VHDL code required for firmware creation. The GT is designed to synchronize all trigger candidates to arrive at the same time at the logic chip, send all trigger candidates into one chip to make any correlation between them, perform a final OR mask for all algorithm bits and implement prescaler and counter for each algorithm. The conditions for trigger object selection, with possible topological requirements on multi-object triggers, are combined by simple combinatorial logic (AND-OR-NOT) to form the algorithms. The most basic algorithms consist of applying pt or Et thresholds to single objects. The algorithms applied during a given data taking period represent the complete physics trigger. As a last step, the algorithms are combined by a final OR function to generate a L1A signal that initiates data acquisition and subsequently forwards the data to the High Level Trigger software. The present trigger electronics will reach its performance limits when LHC exceeds its nominal luminosity. Keeping the trigger efficient at higher luminosities will require higher granularity and more sophisticated trigger algorithms in the Level-1 Trigger. The calculation of the invariant mass or the transverse mass of two or several input objects is designed, along with other arithmetic operations. These calculations could be made by direct floating-point operations using DSPs in the FPGA. Such very specific algorithms will be needed to better suppress the backgrounds and improve flexibility in dealing with changing requirements, thus allowing the selection of more interesting physics data at growing luminosity. Operational experience in developing trigger menus from the first LHC run has shown that the number of trigger algorithms increased as the luminosity and pile-up increased, as a greater use of “cross triggers” (correlated selections of multiple objects) were used to maintain lower Et and pt thresholds on the constituent objects than when each object is selected separately for the same trigger rate. Therefore the total number of possible algorithms is not constrained in the future. Moreover the firmware should be tested systemically based on short-term and long-term test strategies based on architecture of a distributed testing framework – the Test Development Framework (TDF). The TDF will replace the existing heterogeneous testing procedures and help reducing both maintenance and complexity of operation tasks of GT.

Primary author

Dr Babak Rahbaran (Austrian Academy of Sciences (AT))

Co-authors

Herbert Bergauer (Austrian Academy of Sciences (AT)) Johannes Wittmann (Austrian Academy of Sciences (AT))

Presentation materials