Future Computing Platforms for Science in a Power Constrained Era

14 Apr 2015, 17:15
15m
B503 (B503)

B503

B503

oral presentation Track8: Performance increase and optimization exploiting hardware features Track 8 Session

Speaker

Mr Giulio Eulisse (Fermi National Accelerator Lab. (US))

Description

Power consumption will be a key constraint on the future growth of Distributed High Throughput Computing (DHTC) as used by High Energy Physics (HEP). This makes performance-per-watt a crucial metric for selecting cost-efficient computing solutions. For this paper, we have done a wide survey of current and emerging architectures becoming available on the market including x86-64 variants, ARMv7 32-bit, ARMv8 64-bit, Many-Core and GPU solutions, as well as newer System-on-Chip (SoC) solutions. We compare performance and energy efficiency using an evolving set of standardized HEP-related benchmarks and power measurement techniques we have been developing. We evaluate the potential for use of such computing solutions in the context of DHTC systems, such as the Worldwide LHC Computing Grid (WLCG).

Primary authors

Mr David Abdurachmanov (Vilnius University (LT)) Mr Giulio Eulisse (Fermi National Accelerator Lab. (US)) Mr Peter Elmer (Princeton University (US)) Mr Robert Knight (Princeton University (US))

Presentation Materials