The Application of DAQ-Middleware to the J-PARC E16 Experiment

14 Apr 2015, 18:00
15m
Village Center (Village Center)

Village Center

Village Center

oral presentation Track1: Online computing Track 1 Session

Speaker

Mr Eitaro Hamada (High Energy Accelerator Research Organization (KEK))

Description

**1. Introduction** We developed a DAQ system of the J-PARC E16 Experiment by using the DAQ-Middleware. We evaluated the DAQ system and confirmed that the DAQ system can be applied to the experiment. The DAQ system receives an average 660MB/spill of data (2-seconds spill per 6 seconds cycle). In order to receive such a large quantity of data, we need a network-distributed system. DAQ-Middleware is a software framework of a network-distributed DAQ system. Therefore, the framework is a useful tool for the DAQ system development. In our talk, we are going to talk about useful features of DAQ-Middleware, an architecture and DAQ performance of the J-PARC E16 Experiment DAQ system. **2. The J-PARC E16 Experiment** The aim of the J-PARC E16 Experiment is to measure mass spectra of vector mesons in nucleus using electron pair decays with a huge statistics. For such purpose, a high intensity proton beam is used and the interaction rate of the experiment becomes $1\times10^{10}$. To cope with such high intensity and the rate, we plan to use the Gas Electron Multiplier (GEM) Tracker and strip read outs. Figure1 shows the estimation of data transfer to DAQ PCs. ![Estimation of data transfer to DAQ PCs][1] **3. DAQ-Middleware** DAQ-Middleware is a software framework of a network-distributed DAQ system. The framework consists of some software components called DAQ-Components. The framework provides the basic functionalities, such as communication between DAQ-Components, transferring data, starting and stopping the DAQ system. DAQ-Components can be set on separate computers. **4. DAQ system for the E16 Experiment** The DAQ system performs following functions. - store all data on storage devices - build and monitor event data from a part of all events Figure2 shows architecture of an entire DAQ system. ![Architecture of an entire DAQ system][2] The DAQ system consists of two stages. 1st stage PCs read and store all data. The 2nd stage PC builds and monitors event data from a part of all events. Figure3 shows DAQ-Component architecture on one 1st stage PC. ![1st stage for the DAQ system][3] Blue boxes of the figure represent DAQ-Component. Gatherer reads data from one read-out module. Merger receives data from multiple Gatherers and sends the data to Dispatcher. Dispatcher sends data to Logger and Filter. Logger stores data on storage devices. Filter sends data, which meet specific conditions, to a next DAQ-Component on the 2nd stage PC. 1st stage consists of multiple PCs which have these DAQ-Components. Figure4 shows DAQ-Component architecture on one 2nd stage PC. ![2nd Stage for the DAQ system][4] Blue boxes of the figure represent DAQ-Component. Merger receives data from multiple Filters on the 1st stage PC and sends the data to Eventbuilder. This Merger is the same as one of the 1st stage PC. Eventbuilder builds event data from received data. Monitor analysis and monitor the event data. **5. Evaluation for the DAQ System** Because we did not have enough PCs, we evaluated 1st stage and 2nd stage separately. ![Specification of evaluation PC][5] **5.1 1st stage evaluation** ![The environment of 1st stage evaluation][6] We measured maximum throughput of one 1st stage PC. Figure6 shows the environment of the evaluation. Because we did not have read-out modules, we used the emulators instead of those. Data format of the emulators was the same as that of the read-out modules. We installed DAQ-Components of the 1st stage to an evaluation PC. Figure5 shows the specification of the evaluation PC. We prepared the 2nd stage PC which is installed Skeltonsink. Skeltonsink received data and is used only for 1st stage evaluation. Each emulator sent test data to the evaluation PC at a maximum rate. As shown in Table 1, one event data size is 45KB per one read-out module and event rate is 2000Hz. ![Evaluation result of 1st Stage PC][7] Figure7 shows the evaluation result. The points mean measured value, line means ideal value. When the number of emulators was up to 7, measured value matched ideal value. The result shows the evaluation PC can process up to 7 emulators, when read-out modules send data at a maximum rate. One evaluation PC can process around 600MB/s of data at a maximum. During this evaluation, we observed data loss size. There was no data loss when the number of emulators was up to 7. **5.2 2nd stage evaluation** ![The environment of 2nd stage evaluation][8] We evaluated 2nd stage. Figure8 shows the environment of the evaluation. We installed DAQ-Components of the 2nd stage on the evaluation PC. Figure5 shows specification of the evaluation PC. We assumed that 50 read-out modules transferred 45kB/event of data and event rate was 10 Hz after passing Filter. In this case, the 2nd PC received 22MB/s of data. We confirmed that the evaluation PC was able to process 22MB/s of data losing no data. This result shows the evaluation PC has an enough capability. **5. Conclusion** The DAQ system of the J-PARC E16 Experiment consists of two stages. One evaluation PC on 1st stage can process 600MB/s of data at a maximum. Average total data transfer Rate to DAQ PCs is 330MB/s. Therefore, 1st stage can be developed by one PC or a few PCs. 2nd stage can be developed by one PC. Therefore, we were able to confirm the DAQ system can be applied to the experiment by a few PCs. [1]: http://research.kek.jp/people/ehamada/test3.png [2]: http://research.kek.jp/people/ehamada/figure1.png [3]: http://research.kek.jp/people/ehamada/figure2.png [4]: http://research.kek.jp/people/ehamada/figure3.png [5]: http://research.kek.jp/people/ehamada/table2.png [6]: http://research.kek.jp/people/ehamada/figure5.png [7]: http://research.kek.jp/people/ehamada/figure4.png [8]: http://research.kek.jp/people/ehamada/figure6.png

Primary author

Mr Eitaro Hamada (High Energy Accelerator Research Organization (KEK))

Co-authors

Daisuke Kawama (RIKEN Nishina Center) Hiroshi Sendai (High Energy Accelerator Research Organization (KEK)) Kyoichiro Ozawa (High Energy Accelerator Research Organization (KEK)) Prof. Manobu Tanaka (High Energy Accelerator Research Organization (KEK)) Masahiro Ikeno (High Energy Accelerator Research Organization (KEK)) Satoshi Yokkaichi (RIKEN Nishina Center) Tomonori Takahashi (Research Center for Nuclear Physics, Osaka University) Wataru Nakai (University of Tokyo) Yuhei Morino (High Energy Accelerator Research Organization (KEK)) Yuki Obara (University of Tokyo)

Presentation Materials