Development of GEM trigger electronics for the J-PARC E16 experiment

Not scheduled


1919-1 Tancha, Onna-son, Kunigami-gun Okinawa, Japan 904-0495
poster presentation Track1: Online computing


Yuki Obara (University of Tokyo)


The purpose of the J-PARC E16 experiment is to investigate the origin of hadron mass through the chiral symmetry restoration in nuclear matter. In the experiment, we measure mass spectra of vector mesons in nuclei in the $e^{+}e^{-}$ decay channel with high precision and high statistics. We use a 30 GeV proton beam with high intensity of $10^{10}$ per spill to achieve high statistics and targets of 0.1% interaction length to suppress an electron background caused by $\gamma$ - conversion in the targets. In the spectrometer of the experiment, GEM Trackers (GTR), which are composed of three layers of tracking planes in a magnetic field, are used to measure momenta of the decay electrons in the high rate environment. Hadron Blind Detectors (HBD), which are gas Cerenkov counters using GEM, and Lead Glass Calorimeters (LG) are placed outside the GTR to identify electrons. The $e^{+}e^{-}$ event trigger consists of three-fold coincidence of signals from the most outside GTR, HBD and LG. The number of channels for GTR, HBD and LG is about 620, 940, and 1000, respectively. Efficient trigger system selecting events of $e^{+}e^{-}$ decays from huge background events must be constructed in order to reduce the trigger rate to 1-2 kHz that our DAQ can cope with. We developed new Amplifier-Shaper-Discriminator (ASD) ASICs which can deal with large detector capacitance originating from GEM and have a short shaping time to handle the high rate counting. The naive idea to extract the trigger signal from these GEM detectors, such as GTR and HBD, is utilizing signals of strips or pads on the anode readout plane which are used for tracking or electron identification. This idea requires, however, R&D of complex frontend circuits and a large number of channels for the fast signal outputs. In order to avoid these problems, the trigger signals are picked up from the cathode plane of the induction gap of these GEM chambers, namely, the last GEM foil in the stack. Considering to use the signals from the GEM foil, it is difficult to cope with large capacitance of the order of nF by using normal preamps. Requirements of the trigger electronics for GTR are to cope with the large detector capacitance of about 2 nF, a fast shaping time and a good signal-to-noise ratio for the minimum input charge of 10 fC. The cathode plane of a GEM foil of the most outside GTR, whose size is $300 \times 300 \ \mathrm{mm}^2$, has detector capacitance of about 50 nF. The GEM foil is divided into 24 segments in order to reduce the capacitance to about 2 nF and a counting rate in each segment, and to roughly track charged particles. The rough tracking has an important role of decreasing a background of electrons which do not come from targets. In the forward region of the spectrometer, the maximum hit rate of each segment is expected to be 1-2 MHz. Thus, we set the shaping time to 25 ns corresponding to a pulse width of about 200 ns. The electric circuit of the ASIC was designed to suppress Equivalent Noise Charge (ENC) under $2\times 10^4$ for the input detector capacitance of 2 nF. The ASD ASIC chip satisfying the above requirements has been developed by our group in cooperation with Open-It[1]. A modified version of the ASIC for GTR is used as the electronics of the GEM trigger for HBD. A prototype of a preamp board with the ASIC chips was produced. Size of the board should be enough small to be installed in narrow spaces of GTR modules. One of functions of the preamp board is to convert discriminated digital outputs of the ASIC to parallel LVDS signals which are sent to a trigger merger board (TRG-MRG). Also, the board needs to receive slow control signals from the TRG-MRG to activate and control digital functions of the ASIC. This contribution will report the development status of the GEM trigger system and result of performance test of the ASIC chip. Reference: 1.

Primary author

Yuki Obara (University of Tokyo)


Daisuke Kawama (RIKEN Nishina Center) Eitaro Hamada (High Energy Accelerator Research Organization (KEK)) Hiroshi Sendai (High Energy Accelerator Research Organization (KEK)) Kyoichiro Ozawa (High Energy Accelerator Research Organization (KEK)) M. M. Tanaka (High Energy Accelerator Research Organization (KEK)) Masahiro Ikeno (High Energy Accelerator Research Organization (KEK)) Satoshi Yokkaichi (RIKEN Nishina Center) Tomohisa Uchida (High Energy Accelerator Research Organization (KEK)) Tomonori Takahashi (Research Center for Nuclear Physics (RCNP)) Wataru Nakai (University of Tokyo, RIKEN Nishina Center) Yuhei Morino (High Energy Accelerator Research Organization (KEK))

Presentation materials