Preliminary Design Review (PDR) for NSW Electronics

Europe/Zurich
various rooms (CERN)

various rooms

CERN

Lorne Levinson (Weizmann Institute of Science (IL)), Philippe Farthouat (CERN), Stephanie Ulrike Zimmermann (Albert-Ludwigs-Universitaet Freiburg (DE))
    • 09:00 19:00
      Monday 9 February: On-detector Electronics 40/S2-C01 - Salle Curie

      40/S2-C01 - Salle Curie

      CERN

      27
      Show room on map
      • 09:00
        Review Procedure 10m
        Speaker: Philippe Farthouat (CERN)
      • 09:10
        Review Scope. Organisation. NSW Schedule and Constraints on Electronics 20m
        Speaker: Stephanie Ulrike Zimmermann (Albert-Ludwigs-Universitaet Freiburg (DE))
        Slides
      • 09:35
        NSW Electronics Overview 20m
        including latency
        Speaker: Lorne Levinson (Weizmann Institute of Science (IL))
        Slides
      • 10:00
        Background and Luminosity Requirements. Hit Rates 20m
        Speaker: Daniel Lellouch (Weizmann Institute of Science (IL))
        Slides
      • 10:25
        Coffee 10m
      • 11:00
        MM Frontend Bord 30m
        Speaker: Kenneth Johns (University of Arizona (US))
        Slides
      • 12:15
        Lunch 1h
      • 13:15
        sTGC Frontend Board 30m
        Speaker: Liang Han (Univ. of Science & Tech. of China (CN))
        Slides
      • 14:45
        Grounding Strategy and EMC 20m
        Speaker: John Nathaniel Oliver (Harvard University (US))
        Slides
      • 15:25
        Coffee 15m
      • 15:45
        FEB ASICs: TDS 20m
        Speaker: Jinhong Wang (University of Michigan (US))
        Slides
      • 16:15
        FEB ASICs: ART 20m
        Speaker: Sorin Martoiu (IFIN-HH Bucharest (RO))
        Slides
      • 17:15
        Reviewers' Closed Session 1h
    • 09:00 19:00
      Tuesday 10 February: On-detector Electronics 60/6-015 - Room Georges Charpak (Room F)

      60/6-015 - Room Georges Charpak (Room F)

      CERN

      19
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      • 09:00
        sTGC Router 20m
        Speaker: Xueye Hu (Umich)
        Slides
      • 10:00
        sTGC pad trigger 20m
        Speaker: Riccardo Vari (Universita e INFN, Roma I (IT))
        Slides
      • 10:45
        Coffee 15m
      • 11:00
        L1DDC Card 20m
        Speaker: Theodoros Alexopoulos (National Technical Univ. of Athens (GR))
        Slides
      • 12:00
        Lunch 1h 10m
      • 13:15
        MM ADDC Card 20m
        Speaker: Lin Yao (Brookhaven National Laboratory (US))
        Slides
      • 14:15
        LV Power 20m
        Speaker: Dante Amidei (University of Michigan (US))
        Slides
      • 15:30
        Coffee 15m
      • 15:45
        VMM3 Readout and ROC ASIC Requirements/Specs 20m
        Speakers: Lorne Levinson (Weizmann Institute of Science (IL)), Sorin Martoiu (IFIN-HH Bucharest (RO))
        Slides
      • 17:15
        Reviewers' Closed Session 1h
    • 09:00 17:30
      Friday 13 February: Trigger Processors 40/S2-D01 - Salle Dirac

      40/S2-D01 - Salle Dirac

      CERN

      27
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      • 09:00
        NSW Trigger Processor Overview 30m
        overview of NSW trigger system; interface to sector logic incl. data format, replication; compatibility with phase 2; Latency; project organization incl. schedule and responsibilities
        Speaker: Joao Barreiro Guimaraes Da Costa (Harvard University (US))
        Slides
      • 10:00
        sTGC Interface and Trigger Algorithm 20m
        incl. performance and testing
        Speaker: Julia Narevicius (Weizmann Institute of Science (IL))
        Slides
      • 10:45
        Coffee 15m
      • 11:00
        MicroMegas Interface and Trigger Algorithms 20m
        including performance and testing
        Speaker: David Lopez Mateos (Harvard University (US))
        Slides
      • 11:40
        Lunch 1h
      • 12:40
        Ancillary Functions 20m
        Speaker: Lorne Levinson (Weizmann Institute of Science (IL))
        Slides
      • 13:20
        Hardware Platforms: LAr/Stony Brook Option 20m
        Speaker: John David Hobbs (State University of New York (US))
        Slides
      • 13:55
        Hardware Platform: SRS/Bucharest Option 20m
        Speaker: Sorin Martoiu (IFIN-HH Bucharest (RO))
        Slides
      • 14:30
        Hardware Selection Criteria 20m
        Speaker: Joao Barreiro Guimaraes Da Costa (Harvard University (US))
        Slides
      • 15:15
        Reviewers' Closed session 1h