Jun 5 – 10, 2016
Padova, Italy
Europe/Rome timezone

FPGA baseline restorer based on high-speed ADC in particle emission rate measurement system

Jun 10, 2016, 10:30 AM
2h
Centro Congressi (Padova)

Centro Congressi

Padova

Poster presentation Data Acquisition Poster Session 2

Speaker

Mr Zheng Tu (USTC, State Key Laboratory of Particle Detection and Electronics (IHEP & USTC))

Description

A baseline restorer has been implemented with FPGA in 2πα and 2πβ particle emission rate measurement system. The signal of the detector was digitalized by 100MHz ADCs before transferred into the FPGA. The data was transformed into first-order differential and second-order differential data flow in the FPGA for the discrimination of the baseline voltage. The original data and restored data were uploaded to the PC in real-time with only dozens of cycles’ delay. Comparison was made by the plots of signal wave for both original data and restored data. And the influence to the emission rate was also discussed. Results indicated that the FPGA baseline restorer was successfully achieved with little distortion of signal wave and it made help to reduce the error counts.

Primary author

Mr Zheng Tu (USTC, State Key Laboratory of Particle Detection and Electronics (IHEP & USTC))

Co-authors

Mr Hongwei Yu (USTC, State Key Laboratory of Particle Detection and Electronics (IHEP & USTC)) Prof. Kezhu Song (USTC, State Key Laboratory of Particle Detection and Electronics (IHEP & USTC)) Mr Zhiguo Ding (USTC, State Key Laboratory of Particle Detection and Electronics (IHEP & USTC))

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