Jun 5 – 10, 2016
Padova, Italy
Europe/Rome timezone

Register-Like Block RAM: Implementation, Testing in FPGA and Applications for High Energy Physics Trigger Systems

Jun 7, 2016, 8:30 AM
30m
Centro Congressi (Padova)

Centro Congressi

Padova

Oral presentation Front End Electronics and Fast Digitizers DAQ 1 / Front End Electronics

Speaker

Jinyuan Wu (Fermi National Accelerator Lab. (US))

Description

In high energy physics experiment trigger systems, block memories are utilized for various purposes, especially in indexed searching algorithms. It is often demanded to globally reset all memory locations between different events which is a feature not supported in regular block memories. Another common demand is to be able to update the contents in any memory location in a single clock cycle. These two demands can be fulfilled with registers but the cost of using registers for large memory is unaffordable. In this paper, a register-like block memory design scheme is presented, which allows updating memory locations in single clock cycle and effectively resetting entire memory within a single clock. The implementation and test results are also discussed.

Primary author

Jinyuan Wu (Fermi National Accelerator Lab. (US))

Presentation materials