Jun 5 – 10, 2016
Padova, Italy
Europe/Rome timezone

Readout electronics for Belle II imaging Time of Propagation detector

Jun 7, 2016, 3:00 PM
1h 30m
Centro Congressi (Padova)

Centro Congressi

Padova

Poster presentation Poster session 1

Speaker

Dr Dmitri Kotchetkov (University of Hawaii at Manoa)

Description

Belle II experiment at SuperKEKB collider opens a new era in beauty physics. To satisfy demands of Belle II improved particle identification, a novel 8192-channel imaging Time of Propagation (iTOP) detector is being built. In iTOP passage of hadrons through quartz panels generates Cerenkov light, which, after multiple reflections, gets collected by 16-channel microchannel plate photomultipliers (MCP-PMTs). Every photomultiplier anode wire is inserted in an individual socket of a so-called front board, which is parallel to the MCP-PMT back surface. The signals are routed to the pads mounted on the back plane of the front board. Two MCP-PMTs are served by one front board; thus 2x2 two MCP-PMT arrays with two connected front boards collect signals from 128 iTOP channels. At the heart of the iTOP readout system there is a custom designed Application Specific Integrated Circuit (ASIC) with a primary function to sample the amplified waveforms collected from the anodes. Sampling is done by switched-capacitor arrays that perform Wilkinson 12-bit analog-to-digital conversion, with one ADC bit corresponding to about 2 mV. Every ASIC digitizes 8 channels. Four ASICs are hosted by a so-called ASIC carrier board. The ASIC carrier board thus reads out 32 photomultiplier channels. Pogo pin assemblies are mounted at the edge of every ASIC carrier board. The pogo pins (one for each anode) are pressed against the pads of the front board; this way the photomultiplier waveforms get broadcasted to the ASIC carrier board. Then the input waveforms are amplified and later digitized. The digitization in four ASICs of every carrier board is controlled by Zynq XC7Z030 FPGA. Four ASIC carrier boards are interconnected, and one of the ASIC carrier boards is connected to a Standard Control Read-Out Data (SCROD) board which collects the data from four carrier boards. The main component of the SCROD board is Zynq XC7Z045 FPGA which controls the data collection and transfer, as well as triggering and clock distribution. A set of interconnected four ASIC carrier boards and one SCROD board, “a board stack”, represents 128-channel standalone front-end readout system. One iTOP module is read out by 16 MCP-PMTs, thus four board stacks are attached to one module and serve 512 iTOP channels. One high voltage divider is attached to every board stack and serves 8 MCP-PMTs. In total, 332 ASIC carrier boards and 84 SCROD boards were fabricated, tested and integrated in the board stacks (the quantities include spares). Performance of the individual ASIC carriers and of the board stacks was evaluated by a variety of measurements. Particularly, the time resolution of the ASIC channels from measuring 20 ns time difference between two 1.5 V analog 7 ns pulses was found to be about 30 ps. Consequently, the time resolution of the ASIC channels coupled with the MCP-PMTs at a laser test bench was found to be about 70 ps. Integration of the board stacks in the iTOP modules is underway.

Primary author

Dr Dmitri Kotchetkov (University of Hawaii at Manoa)

Co-authors

Mr Christopher Ketter (University of Hawaii at Manoa) Mr Curtis McLellan (University of Hawaii at Manoa) Dr Gary Varner (University of Hawaii at Manoa) Mr Julien Cercillieux (University of Hawaii at Manoa) Dr Luca Macchiarulo (University of Hawaii at Manoa) Mr Marc Rosen (University of Hawaii at Manoa) Mr Matthew Andrew (University of Hawaii at Manoa) Mr Roy Tom (University of Hawaii at Manoa) Dr Ziru Sang (University of Hawaii at Manoa)

Presentation materials