Jun 5 – 10, 2016
Padova, Italy
Europe/Rome timezone

High Speed Ethernet Application for the Trigger Electronics of the New Small Wheel

Jun 7, 2016, 3:00 PM
1h 30m
Centro Congressi (Padova)

Centro Congressi


Poster presentation Fast Data Transfer Links and Networks Poster session 1


Kun Hu (University of Science and Technology of China)


The ATLAS detector will be upgraded in 2018. The main focus of the Phase-I ATLAS upgrade is on the Level-1 trigger, replacing the present muon small wheel (SW) with the "new small wheel(NSW)", which consists of small thin gap chamber(sTGC) and micromegas (MM). A versatile application-specific integrated circuit(ASIC), the VMM chip, has been developed to read out the signals of the sTGC and MM. The VMM has 64 channels. In order to test the performance of the VMM, high data transfer rate is needed. Meanwhile, it is required to implement the multi-board interconnection. We understand that a programmable platform would better suit our needs. It is proposed to apply the high-speed Ethernet-based network for the testing system, the high performance and full programmability of the network are our mainly considered. We design and implement a test platform named the Gigabit Ethernet Module(GEM). The core of the GEM is two layer protocol only for minimal network latency and minimal packet loss, meaning that all data transfers will be handled by Ethernet switches in Field Programmable Gate Array(FPGA). The main task of the GEM is to perform a communication with computer, which receives data from the computer and transfers data to the computer via Ethernet with the help of the MAC(media access control) protocol, which is a hardware implementation on a FPGA device, enabling it to achieve high speed data transfers and low data latency. We conducted performance tests on GEM, and the test result shows that the transfer rate can reach up to 926Mbps. Long term stability of the GEM is also tested, there is no errors for continuous operating two and an half hours. Also, the packet loss is tested in real time by embedding a sequence number into each packet sent to the computer, no errors have been observed. Subsequently, the GEM is applied in the pad front end board (pFEB) and the thin gap chamber simulation signal generator (SG). This paper introduces the implementation of the GEM, as well as its applications. The features of the systems are described in detail.

Primary author

Mr Houbing Lu (University of Science and Technology of China)


Prof. Feng Li (University of Science and Technology of China) Prof. Ge Jin (University of Science and Technology of China) Kun Hu (University of Science and Technology of China) Prof. Liang Han (University of Science and Technology of China) Mr Xu Wang (University of Science and Technology of China)

Presentation materials