Jun 5 – 10, 2016
Padova, Italy
Europe/Rome timezone

A JESD204B-compliant Architecture for Remote and Deterministic-Latency Operation

Jun 9, 2016, 11:00 AM
Centro Congressi (Padova)

Centro Congressi


Oral presentation Fast Data Transfer Links and Networks RTA 1


Dr Raffaele Giordano (Universita' degli Studi di Napoli "Federico II" and INFN)


High-speed analog-to-digital converters (ADCs) are key components in a huge variety of systems, such as wireless infrastructure transceivers, software defined radios, radar, secure communications, medical imaging systems and trigger and data acquisition (TDAQ) systems of Nuclear and Sub-nuclear Physics experiments. In fact, the usage of high-speed ADCs for digitizing analog pulses produced by the front-end electronics opens the way to a fully digital processing, which can be implemented by means of application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). Over the last decades, the sample rate and dynamic range of high-speed ADCs underwent a continuous growth and it required the development of suitable interface protocols. In order to overcome bandwidth limitations of previous standards and to simplify the printed circuit board routing, the Joint Electron Device Engineering Council has proposed the JESD204B serial interface protocol. JESD204B supports data rates of up to 12.5Gbps per serial lane and foresees dedicated features to guarantee a deterministic timing of the conversion and to support the synchronization of multiple converters in the same system. The timing predictability of the protocol is of great interest for TDAQ systems, where it is often required to operate the whole apparatus synchronously in order to preserve critical trigger information and timing-related data. It is important to note that JESD204B is designed for local operation, i.e. the data producer and consumer chips are meant to be on the same board or anyway at distances of the order of few centimeters, while TDAQ systems may require the converter to be remote (e.g. on-detector) with respect to the logic receiving the data (e.g. off-detector). In this work, we present an original JESD204B-compliant architecture we designed, which is able to operate an analog-to-digital converter in a remote fashion. Our design includes a deterministic-latency high-speed serial link, which is the only connection between the local and remote logic of the architecture and which preserves the deterministic timing features of the protocol. By means of our solution it is possible to read data out of several converters, even remote to each other, and keep them operating synchronously. Our link also supports forward error correction (FEC) capabilities, in the view of the operation in radiation areas (e.g. on-detector in TDAQ systems). We discuss an implementation of our concept in a latest generation FPGA (Xilinx Kintex-7 325T), its logic footprint, frequency performance and power consumption. We present measurements of the timing jitter and latency stability of JESD204B timing-critical signals forwarded over the link. We discuss the radiation-effect mitigation strategies we adopted for protecting the firmware in the on-detector FPGA, such as triple modular redundancy and configuration scrubbing. We also describe a demo application of our architecture with a high-speed ADC running a 16-bit dual channel conversion at 370 Msps corresponding (7.4 Gbps line rate).

Primary authors

Prof. Alberto Aloisio (Universita' degli Studi di Napoli "Federico II" and INFN) Dr Raffaele Giordano (Universita' degli Studi di Napoli "Federico II" and INFN) Sabrina Perrella (Universita e INFN, Napoli (IT)) Dr Vincenzo Izzo (INFN Sez. di Napoli)

Presentation materials