Jun 5 – 10, 2016
Padova, Italy
Europe/Rome timezone

NaNet: FPGA-based Network Interface Cards Implementing Real-time Data Transport for HEP Experiments

Jun 7, 2016, 3:00 PM
1h 30m
Centro Congressi (Padova)

Centro Congressi

Padova

Poster presentation Real Time System Architectures and Intelligent Signal Processing Poster session 1

Speaker

Michele Martinelli (INFN)

Description

NaNet is a modular design of a family of FPGA-based PCIe Network Interface Cards implementing low-latency, real-time data transport between its network channels and the the host CPU and GPU accelerators memories. The design feature a network stack protocol offloading module that operating in conjunction with a high performance PCIE Gen2/3 X8 core yields a low and predictable communication latency, making NaNet suitable for real-time applications. A reconfigurable processing module is also available to implement application-specific processing on inbound/outbound data streams with highly reproducible latency. As of now NaNet design has been specialized in the NaNet-1 (single 1GbE port) and NaNet-10 (four 10GbE ports) configurations employed in the GPU-based real-time trigger of the CERN NA62 experiment, and in the NaNet3 (four 2.5 Gbit optical channels) configuration adopted in the data acquisition system of the KM3NeT-Italia underwater neutrino telescope. Assessment of the real-time characteristics and performances of the resulting systems will be provided and analyzed.

Primary authors

Alessandro Lonardo (Universita e INFN, Roma I (IT)) Andrea Biagioni (INFN) Mrs Francesca Lo Cicero (INFN Sezione di Roma) Michele Martinelli (INFN) Mr Ottorino Frezza (INFN Sezione di Roma) Mr Pier Stanislao Paolucci (INFN Sezione di Roma) Piero Vicini (Universita e INFN, Roma I (IT)) Roberto Ammendola (Universita e INFN Roma Tor Vergata (IT))

Co-authors

Mrs Elena Pastorelli (INFN Sezione di Roma) Gianluca Lamanna (Istituto Nazionale Fisica Nucleare Frascati (IT)) Luca Pontisso (Universita di Pisa & INFN (IT))

Presentation materials