Jun 5 – 10, 2016
Padova, Italy
Europe/Rome timezone

The study of strip Readout Prototype for ATLAS Phase-I muon Trigger upgrade

Jun 10, 2016, 10:30 AM
2h
Centro Congressi (Padova)

Centro Congressi

Padova

Poster presentation Data Acquisition Poster Session 2

Speaker

Feng Li (Univ. of Science & Tech. of China (CN))

Description

ATLAS is one of the four experiments at Large Hadron Collider (LHC).LHC will be upgraded in the next several years aiming to new physics study. ATLAS experiment will fulfill Phase-I upgrade by 2018. The current ATLAS muon end-cap system (Small Wheel, SW) will be replaced with the New Small Wheel (NSW). The NSW is a set of precision tracking and trigger detectors able to work at high rates with excellent real-time spatial and time resolution. The small-strip Thin Gap Chamber (sTGC) will devote to trigger function in NSW. sTGC contains pad, wire and strip readout. The pads are used through a 3-out-of-4 coincidence to identify muon tracks roughly pointing to the interaction point (IP). They are also used to define which strips need to be readout to obtain a precise measurement in the bending coordinate for the event selection. This paper presents the study of sTGC strip Readout Prototype, and it is named strip Front End Board (sFEB). It will accept the pad trigger, which is the external trigger from the trigger unit through a Mini-SAS connector, to define the regions-of-interest for strips readout. Strip signals are received by a VMM2 ASIC which can handle the signals with the capacity of 64 inputs, and output the trigger data and raw data of hit events. The VMM2 trigger data will be transmitted to a Trigger Data Serializer (TDS) ASIC which is still under development. The raw data will be sent to Read-Out Controller (ROC) ASIC which is also not ready yet.The core of sFEB is based on a Kintex-7 FPGA, which is configured by a Serial Peripheral Interface (SPI) flash. The FPGA also accomplish the functions of TDS and ROC ASICs, the configuration and data readout of up to eight VMM2s, and all the data transceiver with PC through a commercial Ethernet chip. Eight VMM2s, which are interconnected using a daisy chain, are used to read out the strip signals from the sTGC detector.The overall sFEB has the ability to handle up to 512 channel strip signals. The prototype also enables us to test and understand VMM2, which can help optimize the design of sFEB for the next version.

Primary author

Feng Li (Univ. of Science & Tech. of China (CN))

Co-authors

Prof. Ge Jin (Univ. of Science & Tech. of China (CN)) Mr Hang Yang (Univ. of Science & Tech. of China (CN)) Mr Houbing Lu (Univ. of Science & Tech. of China (CN)) Dr Kun Hu (Univ. of Science & Tech. of China (CN)) Prof. Liang Han (Univ. of Science & Tech. of China (CN)) Ms Tianru Geng (Univ. of Science & Tech. of China (CN)) Ms Xinxin Wang (Univ. of Science & Tech. of China (CN)) Mr Xu Wang (Univ. of Science & Tech. of China (CN))

Presentation materials