Speaker
Paolo Durante
(CERN)
Description
The LHCb experiment is designed to study differences between particles and anti-particles as well as very rare decays in the charm and beauty sector at the LHC. The detector will be upgraded in 2019 and a new trigger-less readout system has to be implemented in order to significantly increase its efficiency.
In the new scheme, event building and event selection are carried out in software and the event filter farm receives all data from every LHC bunch-crossing. Another feature of the system is that data coming from the front-end electronics is delivered directly into the event builders memory through a specially designed PCIe card called PCIe40.
The PCIe40 board handles the data acquisition flow as well as the distribution of fast and slow controls to the detector front-end electronics. It embeds one of the most powerful FPGAs currently available on the market with 1.2 million logic cells. The board has a bandwidth of up to 490 Gbits/s in both input and output over optical links and up to 100 Gbits/s over the PCI Express bus to the CPU.
We will present how data flows through the board and to its associated server during event building. We will focus on specific issues regarding the design of the different firmwares being developed for the FPGA, showing how to manage flows of 100 Gbits/s, and all the techniques put in place when different firmwares are developed by distributed teams of sub-detector experts.
Primary author
Jean-Pierre Cachemiche
(Centre National de la Recherche Scientifique (FR))
Co-authors
Federico Alessio
(CERN)
Guillaume Vouters
(Centre National de la Recherche Scientifique (FR))
Niko Neufeld
(CERN)
Paolo Durante
(CERN)
Rainer Schwemmer
(CERN)
Renaud Le Gac
(CPPM CNRS/IN2P3)
