cRIO-White Rabbit status update and WR roadmap
Synchronisation needs (EPFL) / cRIO-White Rabbit status update / WR roadmap (CERN)
Presentations and discussions with interest groups from EPFL, CERN and NI Energy Segment manager, GE Florence, Italy (by Skype).
Connect by Skype to: labsyste
Adam Artur Wujek
Adriaan Rijllart
Augusto Mandelli
Daniel Florin
Daniele Colangelo
Emanuele Freddi
Grzegorz Daniluk
Javier Serrano
Jean-Yves Le Boudec
Joe Woodford
Joel Lahaye
Jorge Blanco Alonso
Joseph Tagg
Kevin Develle
Luigi Giorgi
Maciej Marek Lipinski
Marco Pignati
Mario Paolone
Miroslav Popovic
Mohiuddin Maaz
Nicolas Pasquier
Odd Oyvind Andreassen
Paolo Romano
Sergio Barreto
Tesfay Teklemariam Tsegay
cRIO-White Rabbit status update and WR roadmap (23 Jun 2015)
Present: Odd Oyvind Andreassen; Sergio Barreto; Jorge Blanco Alonso; Grzegorz Daniluk; Kevin Develle; Daniel Florin; Emanuele Freddi; Luigi Giorgi; Joel Lahaye; Jean-Yves Le Boudec; Maciej Marek Lipinski; Mohiuddin Maaz; Augusto Mandelli; Mario Paolone; Nicolas Pasquier; Marco Pignati; Miroslav Popovic; Adriaan Rijllart; Paolo Romano; Javier Serrano; Joseph Tagg; Tesfay Teklemariam Tsegay; Joe Woodford; Adam Artur Wujek
Chaired by: Rijllart, Adriaan
Time synchronisation needs in phasor measurement units for the real-time monitoring of power grids - by Prof. Mario Paolone
Phasor Measurement Units will require accuracies of ppm of radians and response times of a few ms. This calls for synchronisation of distributed metering systems with jitters of few tens of ns.
Update on the WR status and roadmap - Javier Serrano
Switch status: Version 4.1.2 of gate ware released in December 2014. Supports 3.4 hardware, VLANs and statistics. Still some bugs at high loads. To be improved.
Node status: Several applications are operational using SPEC, SVEC (and SPEXI)*. For instance in LHC instability studies (and LEIR kicker magnets)*.
Roadmap Switch: fix bugs, complete SNMP support, add monit support to detect and restart stopped processes. Release in July 2015. For 2016: clock and data switch-over, clock hold-over.
Roadmap Node: fix bugs, improve WR Node Core, RF distribution over WR. Medium term: integrate WR into CERN's General Machine Timing system. Integrate new RISC-V processor core into WRNC.
Status of the cRIO-WR module - Adriaan Rijllart
cRIO-WR module designed and built by Daniel Florin of the University of Zürich. Entered design in CERN's open hardware repository. A series of 10 modules has been produced by INCAA on request of Adriaan. After optimisation of the FPGA driver for the module testing shows that time stamping a known input pulse (WR PPS) we obtain a delay of 850 ns without any measurable jitter, clocking the cRIO FPGA at 160 MHz. At 40 MHz we get 990 ns delay and 3.3 ns jitter.
Roadmap: Dedicated reference clock output, reducing operating power, solve persistent memory writing bug and review board design by CERN DEM service.
Discussion: Mario Paolone is interested to get a WR switch at the EPFL. Javier offered help during the setup phase. Adriaan is interested in the power storage at the EPFL. Positive feedback from Fabio Mussi, connected by Skype, who is interested to collaborate with CERN on WR in the future.
Meeting finished with a visit to the WR lab where the cRIO-WR was demoed by Kevin Develle.
* Added by Adriaan to complete the information.