Programmable Logic and Specialities memories overview

by Philippe Larcher (CYPRESS)

Wednesday 26 Jan 2000, 14:00 → 14:15 Europe/Zurich

CERN

'CPLDs at FPGA Densities' Built with an advanced 0.18µ SRAM process, The Delta 39K family offers densities from 15K to 350K useable gates, including the world's largest CPLD with 5376 macrocells. Delta 39K CPLDs provide more than five times the amount of embedded RAM compared to any other programmable logic. Additionally, on-chip, dedicated FIFO flag and Dpr control logic finally allows you to build fast and efficient memory functions without compromising any macrocell logic. There is also a spread aware PLL, which allows clock multiplication, division, and skew adjustment. 'FIFO and MultiPORT RAM' Cypress has introduced families of higher performance, deeper and wider speciality memory devices over the last three years, gaining market share and enhancing its speciality memory portfolio. The company's emphasis on bandwidth addresses the demands of local area networks (LANs), wide area networks (WANs), and storage attached networks (SANs), all of which are used to transfer and store the rapidly expanding amount of data that travels over the Internet. Bandwidth can be increased by several methods including increasing the number of access ports, widening the word width of devices, and/or increasing clock speeds. Cypress has and will continue to use all three of these methods to extend its leadership with new architectures optimised for bandwidth. The company is currently at the 10 Gbps barrier and plans to achieve 25 Gbps later this year.

Organiser(s): S. Shearer / SPL / 76360

Note: Languages: French, English