1) VFC decisions:

• The base-line for finishing the VFC design are DDR3L RAM chips in single density.
• There are few remaining issues with this design, one important outstanding issue is the clock signal generation for the RAM chips. (action: Andrea)
• We aim again at a prototype series production of about 40 units. We use the residual of the existing contract and we convince FI to place the new commitment to the same company. (action: Andrea, Thibaut)
  We aim to have the first boards at CERN in January 2016, given some to users in March 2016.
• Andrea contacts the vendor of DDR3 (noL) chips and confirms the availability of these chips for spring 2016.
  • If not he orders 400 pieces straight away for a price below 5 KCHF

2) DI update (Jiri Kral)

• First tests with ICT/WCM in LHC point 4
• Correlation with DC BCT performed - below 1% disagreement (low gain)
• Main question is price for the number we need (discussion with FI - David/Rhodri)
• Next steps: hardware/software specifications for FESA tests (Jiri/Stephane Bart)
• Expecting specifications for diamond BLM (Bernd Dehning)

3) Instability Network (Tom Levens)

• Pressure from ABP to get on with it
• BE/RF should normally drive developments (W. Hofle/D. Valuch) - gone quiet
• Head-tail triggering (LeCroy scopes) based on BBQ detection (too sensitive)
• BBQ electronics saturates despite new diodes
• New hardware being developed (VFC (nios kernel)->Ethernet) with FESA3 class (Tom)
• Hope for more results at next MD