TWEPP-09 Topical Workshop on Electronics for Particle Physics

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Sessions*

POSTERS SESSION

Power WG

Plenary Session 5 - Key technologies for present and future optical networks

Parallel Session A5 - ASICS

Parallel Session B3 - Packaging and Interconnects

OPENING 1

OPENING 2

Parallel Session B4 - Power, Grounding and Shielding

TOPICAL

Parallel session A1 - ASICs

Plenary Session 2 - Low Power Analog Design Techniques

Plenary Session 1 - Beam Condition Monitors and Machine-Experiment Interlocks

Parallel session A2 - ASICs

Parallel session B1 - Systems, Installation and Commissioning

MUG

Parallel session B2a - Production, testing and reliability

TUTORIAL - FPGA Tools and Techniques for High Performance Digital Systems (1)

Plenary Session 3 - Buses and boards, making the right choice

Parallel session B2b - Radiation tolerant components and systems

Parallel Session A3 - Trigger

Parallel session A4 - Trigger

Plenary Session 4 - Low Noise Design for Large Detectors

Parallel Session B5 - Optoelectronics and Links

CLOSE OUT

Plenary Session 7 - Reports from WGs

Plenary Session 6 - Programmable Logic, Boards, Crates and Systems

OPTO WG

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Contributions*

3D electronics for hybrid pixel detectors (in session "Parallel Session B3 - Packaging and Interconnects")

A 5 Gb/s Radiation Tolerant Laser Driver in 0.13 um CMOS technology (in session "Parallel Session A5 - ASICS")

A 10-bit 40MS/s pipelined ADC in a 0.13µm CMOS process (in session "POSTERS SESSION")

A 12 µm pitch CMOS Pixel Sensor Designed in the 3DIT for the ILC Vertex Detector (in session "POSTERS SESSION")

A 40 MHz trigger-free readout architecture for the LHCb experiment (in session "POSTERS SESSION")

A digital calorimetric trigger for the COMPASS experiment at CERN (in session "Parallel Session A3 - Trigger")

A Digitally Calibrated 12 bits 35 MS/s Pipelined ADC with a 32 input multiplexer for CALICE Integrated Readout (in session "POSTERS SESSION")

A facility and a web application for real-time monitoring of the TTC backbone status (in session "POSTERS SESSION")

A flash high-precision Time-to-Digital Converter implemented in FPGA technology (in session "Plenary Session 6 - Programmable Logic, Boards, Crates and Systems")

A latchup topology to investigate novel particle detectors (in session "Parallel Session A5 - ASICS")

A low-cost multi-channel analogue signal generator (in session "POSTERS SESSION")

A new paradigm using GPUs for fast triggering and pattern matching at the CERN experiment NA62 (in session "POSTERS SESSION")

A programmable 10 Gigabit injector for the LHCb DAQ and its upgrade (in session "POSTERS SESSION")

A Prototype Front-End Readout Chip for Silicon Microstrip Detectors Using an Advanced SiGe Technology (in session "POSTERS SESSION")

A self triggered amplifier/digitizer chip for CBM (in session "POSTERS SESSION")

A SiGe ASIC Prototype for the ATLAS LAr Calorimeter Front-End Upgrade (in session "Parallel session A2 - ASICs")

A Zero Suppression Micro-Circuit for Binary Readout CMOS Pixel Sensors (in session "POSTERS SESSION")

About 10000 frames per second readout MAPS for the EUDET beam telescope (in session "Parallel session A1 - ASICs")

Access to ASIC Design Tools and Foundry Services at CERN for SLHC (in session "MUG")

Advanced Pixel Architectures for Scientific Image Sensors (in session "Parallel session A1 - ASICs")

AFTER, the Front-End ASIC of the T2K Time Projection Chambers (in session "POSTERS SESSION")

ALICE TPC CONTROL AND READOUT SYSTEM (in session "POSTERS SESSION")

An FPGA-based Emulation of the G-Link Chip-Set for the ATLAS Level-1 Barrel Muon Trigger (in session "POSTERS SESSION")

An integrated DC-DC step-up charge pump and step-down converter in 130 nm technology (in session "POSTERS SESSION")

Analogue Input Calibration of the ATLAS Level-1 Calorimeter Trigger (in session "Parallel Session A3 - Trigger")

Application of a new interconnection technology for the ATLAS pixel upgrade at SLHC (in session "Parallel Session B3 - Packaging and Interconnects")

ASIC buck converter prototypes for LHC upgrades (in session "Parallel Session B4 - Power, Grounding and Shielding")

ASPIC: LSST camera readout chip Comparison between DSI and C&S (in session "POSTERS SESSION")

ATLAS Silicon Microstrip Tracker Operation (in session "POSTERS SESSION")

BAO radio electronic system (in session "Parallel session B1 - Systems, Installation and Commissioning")

Buffer Control Chip (BCC) for the ATLAS Tracker Upgrade (in session "POSTERS SESSION")

Buses and Boards (in session "Plenary Session 3 - Buses and boards, making the right choice")

Characterization of Semiconductor Lasers for Radiation Hard High Speed Transceivers (in session "POSTERS SESSION")

Charge Pump Clock Generation PLL for the Data Output Blocks of the Upgraded ATLAS Front-End in 130nm CMOS (in session "POSTERS SESSION")

CLOSE OUT (in session "CLOSE OUT")

CMD-3 First Level Trigger Infrastructure (in session "POSTERS SESSION")

Commissioning and performance of the Preshower off-detector readout electronics in the CMS experiment (in session "Parallel session B1 - Systems, Installation and Commissioning")

Commissioning of the CSC Level 1 Trigger Optical Links at CMS (in session "POSTERS SESSION")

Commissioning of the DT electronics under magnetic field. (in session "Parallel session B1 - Systems, Installation and Commissioning")

Construction and Performance of a Double-Sided Silicon Detector Module using the Origami Concept (in session "Parallel Session B3 - Packaging and Interconnects")

Data acquisition system for a proton imaging apparatus (in session "Parallel session B1 - Systems, Installation and Commissioning")

DC-DC switching converter based power distribution vs Serial power distribution: EMC strategies for SLHC tracker up-grade (in session "POSTERS SESSION")

Deep-sea data transfer at the KM3NeT neutrino telescope (in session "Parallel session B1 - Systems, Installation and Commissioning")

DEPFET Mini-matrix Readout System (in session "POSTERS SESSION")

Design and measurements of 10 bit pipeline ADC for the Luminosity Detector at ILC (in session "POSTERS SESSION")

Design Considerations for an Upgraded Track-Finding Processor in the Level-1 Endcap Muon Trigger of CMS for SLHC Operations (in session "Parallel session A4 - Trigger")

Design of a module providing trigger information from the CMS Tracker at SLHC (in session "Parallel session A4 - Trigger")

Design of High Dynamic Range Digital to Analog Converters for Calibration of the CALICE readout electronics (in session "Parallel session A2 - ASICs")

Design of the CMS-CASTOR sub detector readout system by reusing existing designs (in session "POSTERS SESSION")

Detector Control System for the Electromagnetic calorimeter in CMS Experiment (in session "POSTERS SESSION")

Development and commissioning of the ALICE pixel detector control system (in session "POSTERS SESSION")

Development of a 16:1 serializer for data transmission at 5 Gbps (in session "POSTERS SESSION")

Development of a high resolution transient recorder (in session "POSTERS SESSION")

Development of new readout electronics for the ATLAS LAr calorimeter at the sLHC (in session "Parallel session B2b - Radiation tolerant components and systems")

Digital Block Implementation Methodology for a 130nm process (in session "MUG")

DIRAC v2: a DIgital Readout Asic for hadronic Calorimeter (in session "Parallel session A2 - ASICs")

Discussion (in session "Power WG")

Discussion (in session "MUG")

e-link: A Radiation-Hard Low-Power Electrical Link for Chip-to-Chip Communication (in session "POSTERS SESSION")

Electronic development for the upgrade of the LHCb Vertex detector. (in session "POSTERS SESSION")

EMC issues for CMS Tracker Upgrade (in session "Power WG")

Error-free 10.7 Gb/s digital transmission over 2 km optical link using an ultra-low-voltage electro-optic modulator (in session "POSTERS SESSION")

Executive Summary

Experiment protection at the LHC and damage limits in LHC(b) silicon detectors (in session "Plenary Session 1 - Beam Condition Monitors and Machine-Experiment Interlocks")

Experimental studies towards a DC-DC conversion powering scheme for the CMS silicon strip tracker at SLHC (in session "Parallel Session B4 - Power, Grounding and Shielding")

Feasibility studies of a Level-1 Tracking Trigger for ATLAS (in session "Parallel session A4 - Trigger")

FPGA Tools and Techniques for High Performance Digital Systems (Tutorial) (in session "TUTORIAL - FPGA Tools and Techniques for High Performance Digital Systems (1)")

FPGA-based Bit-Error-Ratio Tester for SEU-hardened Optical Links (in session "Plenary Session 6 - Programmable Logic, Boards, Crates and Systems")

Framework for Testing and Operation of the ATLAS Level-1 MUCTPI and CTP (in session "Parallel Session A3 - Trigger")

Front-End Electronics for Pixel Detector of the PANDA MVD. (in session "Parallel session A1 - ASICs")

Future operating mode of the group (in session "OPTO WG")

Gossipo-3: a prototype of a Front-end Pixel Chip for Read-out of Micro-Pattern Gas Detectors. (in session "Parallel session A2 - ASICs")

HARDROC, Readout chip of the Digital Hadronic Calorimeter of ILC (in session "Parallel session A2 - ASICs")

Hardware studies for the upgrade of the ATLAS Central Trigger Processor (in session "POSTERS SESSION")

HEP experiments in Japan : The Next Generation (in session "OPENING 2")

High-Speed Serial Optical Link Test Bench Using FPGA with Embedded Transceivers (in session "POSTERS SESSION")

ILC-CLIC (in session "OPENING 2")

Implementing the GBT data transmission protocol in FPGAs (in session "Plenary Session 6 - Programmable Logic, Boards, Crates and Systems")

In-situ performance of the CMS Preshower Detector (in session "Parallel session B1 - Systems, Installation and Commissioning")

Integrated test environment for a part of the LHCb calorimeter (in session "Parallel session B2a - Production, testing and reliability")

Integrated Trigger and Data Acquisition system for the NA62 experiment at CERN (in session "Parallel Session A3 - Trigger")

Interference coupling mechanisms in Silicon Strip Detector – FEE. -CMS tracker “wings”: A leaned lesson for SLHC- (in session "POSTERS SESSION")

Irradiation results of technologies for a custom DCDC converter (in session "Power WG")

Key technologies for present and future optical networks (in session "Plenary Session 5 - Key technologies for present and future optical networks")

KM3NeT Power and Submarine Cable Systems for the kilometre cube Neutrino Telescope (in session "Parallel Session B4 - Power, Grounding and Shielding")

LHCb Level 0 Decision Unit (in session "Parallel Session A3 - Trigger")

Low Noise Design for Large Detectors (in session "Plenary Session 4 - Low Noise Design for Large Detectors")

Low noise, low power front end electronics for pixelized TFA sensors (in session "Parallel session A1 - ASICs")

Low Power Analog Design in Scaled CMOS Technologies (in session "Plenary Session 2 - Low Power Analog Design Techniques")

Low power discriminator for ATLAS pixel chip (in session "POSTERS SESSION")

Low Power SoC Design (in session "TOPICAL")

Measurement of radiation damage of 130nm hybrid pixel detector readout chips (in session "Parallel session B2b - Radiation tolerant components and systems")

Measurement of the performances of a Low-Power Multi-Dynamics Front-End for Neutrino Underwater Telescope Optical Modules (in session "POSTERS SESSION")

Micro-Electronics at In2P3 (in session "OPENING 1")

Mixed-Signal Challenges and Solutions for advanced process nodes (in session "MUG")

Novel charge sensitive amplifier design methodology suitable for large detector capacitance applications (in session "POSTERS SESSION")

OMEGAPIX : 3D electronics chip for pixel readout (in session "POSTERS SESSION")

On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS) (in session "POSTERS SESSION")

PARISROC, a photomultiplier array integrated readout chip (in session "Parallel Session A5 - ASICS")

Passive Optical Networks in Particle Physics Experiments (in session "Parallel Session B5 - Optoelectronics and Links")

Performance and comparison of custom serial powering regulators and architectures for SLHC silicon trackers (in session "Parallel Session B4 - Power, Grounding and Shielding")

Performance of the ABCN-25 readout chip for ATLAS Inner Detector Upgrade (in session "Parallel session A1 - ASICs")

PERFORMANCE OF THE CMS REGIONAL CALORIMETER TRIGGER (in session "Parallel Session A3 - Trigger")

Picosecond time measurement using ultra fast analog memories. (in session "Parallel session B2a - Production, testing and reliability")

Position Measurements with Micro-Channel Plates and Transmission Lines using Pico-second Timing and Waveform Analysis (in session "POSTERS SESSION")

Precise Timing Adjustment for the ATLAS Level1 Endcap Muon Trigger System (in session "Parallel Session A3 - Trigger")

Presentation of the “ROC” chips readout (in session "POSTERS SESSION")

Progress on DC-DC converters for SiTracker for SLHC (in session "Parallel Session B4 - Power, Grounding and Shielding")

Prototype flex hybrid and module designs for the ATLAS Inner Detector Upgrade utilising the ABCN-25 readout chip and Hamamatsu large area Silicon sensors. (in session "Parallel Session B3 - Packaging and Interconnects")

Radiation Hardness of Graded-index Optical Fibre in Sub-Zero Temperature Environments (in session "Parallel Session B5 - Optoelectronics and Links")

Radiation hardness studies of a 130 nm Silicon Germanium BiCMOS technology with a dedicated ASIC (in session "POSTERS SESSION")

Radiation tests on the complete system of the instrumentation of the LHC Cryogenics at the CERN Neutrinos to Gran Sasso (CNGS) test facility (in session "Parallel session B2b - Radiation tolerant components and systems")

Readout and Data Processing Electronics for the Super-Belle Silicon Vertex Detector (in session "POSTERS SESSION")

Recent Advances in Architectures and Tools for Complex FPGA-based Systems (Invited Talk) (in session "Plenary Session 6 - Programmable Logic, Boards, Crates and Systems")

Reduction techniques of the back gate effect in the SOI Pixel Detector (in session "Parallel session A1 - ASICs")

Replacing full custom DAQ test system by COTS DAQ components on example of ATLAS SCT readout (in session "Parallel session B2a - Production, testing and reliability")

Report from MUG (in session "Plenary Session 7 - Reports from WGs")

Report from Opto WG (in session "Plenary Session 7 - Reports from WGs")

Report from Power WG (in session "Plenary Session 7 - Reports from WGs")

Research activities at Pierre & Marie Curie University (in session "OPENING 1")

Roadmap for DC-DC (in session "Power WG")

Roadmap for serial powering (in session "Power WG")

Silicon Photomultiplier integrated readout chip (SPIROC) for the ILC: characterization and mesurements (in session "POSTERS SESSION")

Simple parallel stream to serial stream converter for Active Pixel Sensor readout. (in session "POSTERS SESSION")

Smart Analogue Sampler for the Optical Module of a Cherenkov Neutrino Detector (in session "Parallel Session A5 - ASICS")

SPI test results (in session "Power WG")

Standalone radiation monitors for electronics in High Energy Physics (in session "POSTERS SESSION")

Status and Perspective of Research at IN2P3 (in session "OPENING 1")

STUDY OF RADIATION HARDNESS OF PIN AND VCSEL ARRAYS (in session "Parallel Session B5 - Optoelectronics and Links")

Study Radiation Hardness Performance of PiN diodes for the ATLAS Pixel Detector at SLHC (in session "POSTERS SESSION")

SuperNemo Absolute Time Stamper, a high resolution and large dynamic range TDC for SuperNemo experiment (in session "Parallel Session A5 - ASICS")

System Integration Issues of DC to DC converters in the sLHC Trackers (in session "Parallel Session B4 - Power, Grounding and Shielding")

The 8 bits 100 MS/s pipe line ADC for the INNOTEP project (in session "Parallel Session A5 - ASICS")

The ATLAS ReadOut System - improved performance with the switch-based architecture (in session "POSTERS SESSION")

The Control System for a new Pixel Detector at the sLHC (in session "POSTERS SESSION")

The design of a low power, high speed phase locked loop (in session "POSTERS SESSION")

The Fast Tracker Architecture for the LHC baseline luminosity (in session "POSTERS SESSION")

The First Vertically Integrated MPW Run for HEP (in session "Parallel Session B3 - Packaging and Interconnects")

The future of the LHC programme and machine (in session "OPENING 2")

The GBT project (in session "Parallel Session B5 - Optoelectronics and Links")

The GBT-SCA, a radiation tolerant ASIC for detector control applications in SLHC experiments (in session "POSTERS SESSION")

The GBTIA, a 5 Gbit/s radiation-hard optical receiver for the SLHC upgrades (in session "Parallel Session A5 - ASICS")

The GCT μTCA Matrix Card and its Applications (in session "Parallel session A4 - Trigger")

The Noise Performance of the CMS Detector (in session "Parallel session B1 - Systems, Installation and Commissioning")

The Online Error Control and Handling of the ALICE Pixel Detector (in session "POSTERS SESSION")

The Prompt Trigger of the Silicon Pixel Detector for the ALICE Experiment (in session "POSTERS SESSION")

The Versatile Transceiver Proof of Concept (in session "Parallel Session B5 - Optoelectronics and Links")

Thin, Fully Depleted Monolithic Active Pixel Sensor with Binary Readout based on 3D Integration of Heterogeneous CMOS Layers (in session "Parallel Session B3 - Packaging and Interconnects")

Total dose effects on a deep-submicron SOI technology for Monolithic Pixel Sensor development (in session "POSTERS SESSION")

Trigger Platforms for CMS at the SLHC (in session "Parallel session A4 - Trigger")

Two-Phase Cooling of Targets and Electronics for Particle Physics Experiments (in session "TOPICAL")

Upgrade of the BOC for the ATLAS Pixel Insert-able B-Layer (in session "POSTERS SESSION")

Upgrade of the Cold Electronics of the ATLAS HEC Calorimeter for sLHC: Generic Studies on Radiation Hardness and Temperature Dependence. (in session "POSTERS SESSION")

Versatile Link status report (in session "OPTO WG")

Wafer Screening of ABCN-25 readout ASIC (in session "POSTERS SESSION")

Welcome 1 (in session "OPENING 1")

Welcome 2 (in session "OPENING 1")

A Radiation Tolerant 4.8 Gb/s Serializer for the Giga-Bit Transceiver (in session "POSTERS SESSION")

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