High-speed DAC and ADC boards as important parts of quantum computers are used to control and read out the states of qubits, their manipulation complexity is rapidly increasing as the number of qubits boosts. The low efficiency of communication, imperfections of electronic device and the coherent control of the qubits are gradually highlighted, which have become the bottleneck to scale up the qubits. To address the problems, we present a control and readout solution in this study. We adopted the C/S structure and developed two servers called the ADC server and DAC server which enable rapid physical experiments to implement. The DAC server realized waveform processing engine, which can not only mitigate the imperfections of the DAC itself, but also can compensate the transmission loss of circuit. To simplify the coherent control of device, we extract a logical layer for the server with corresponding physical resources and automatically aligned the timing of different channels. A simple data link layer protocol is designed for the high-bandwidth communication with ADC boards. According to the characteristics of low speed soft-core in FPGA, we design a multi-threaded communication mechanism to improve the overall data transmission efficiency of multiple DAC boards. By using these network optimization strategies, both data transmission rate of ADC and DAC boards can reach hundreds of Mbps.