Jun 9 – 15, 2018
Woodlands Conference Center
America/New_York timezone
**** See you at Real Time 2020 ****

Implementation of a High-Performance Pattern Recognition Associative Memory in an FPGA

Jun 12, 2018, 9:30 AM
Woodlands Conference Center

Woodlands Conference Center

159 Visitor Center Dr, Williamsburg, VA 23185
Oral presentation Large Experiments 4


Jamieson Olsen (Fermi National Accelerator Lab. (US))


Pattern recognition associative memory (PRAM) devices are parallel processing engines which are used to tackle the complex combinatorics of track finding algorithms, particularly for silicon based tracking triggers. PRAM development has been mostly limited to the realm of ASICs, which often leads to lengthy and expensive design cycles. FPGAs allow for quick iterations, making them an ideal hardware platform for designing and evaluating new PRAM features before committing to silicon. The FPGA implementation of PRAMs is also highly desirable for early performance studies; for example, it can bring system interface to maturity much sooner and minimize the number of ASIC design cycles. In this talk we present our new PRAM designs and discuss how logic blocks which were originally developed for ASICs are redesigned to take advantage of modern FPGA architectures to increase both speed and pattern density.

Description Pattern Recognition
Minioral Yes
Country USA
Speaker Jamieson Olsen
Institute FNAL

Primary authors

Jamieson Olsen (Fermi National Accelerator Lab. (US)) James Hoff (Fermi National Accelerator Lab. (US)) Zhen Hu (Fermi National Accelerator Lab. (US)) Sergo Jindariani (Fermi National Accelerator Lab. (US)) Tiehui Ted Liu (Fermi National Accelerator Lab. (US)) Jinyuan Wu (Fermi National Accelerator Lab. (US)) Zijun Xu (SLAC National Accelerator Laboratory (US))

Presentation materials