A fully synchronous programmable pattern generator is often required in modern physics experiments.
Typical cases are experiments that use Charge Coupled Device (CCD) as detectors or the design verification of electronics devices.
Most of the times commercial pattern generators are used but in some specific cases they are not practical or impossible to use. An alternative is to implement a pattern generator on a Field Programmable Gate Array (FPGA).
The proposed design feature 32 outputs a time resolution of 10 ns and a fully programmable structure that allows the generation of patterns from 10 ns to minutes of length. The architecture looks like a simple processor hence the pattern is defined writing a program that resides inside the FPGA’s memory.
A so-called time-slice represents the pattern generator’s basic element. A time-slice is defined by a steady state of the outputs. A pattern is defined by a sequence of time-slices that are concatenated and executed in sequence. A group of time-slices is called function and can contain up to 16 time-slices. 16 different functions can be defined.
The execution order of different functions is written in the program memory by means of instructions or Operation Codes.
The concept of pointers is also implemented to provide high flexibility in writing the program.
The sequence execution time is tightly controlled to ensure a resolution of 10 ns over the entire sequence without glitches and latencies. The design is written in vhdl and can be ported on all kinds of FPGA.