9-15 June 2018
Woodlands Conference Center
America/New_York timezone
**** See you at Real Time 2020 ****

Fixed latency fiber communication for JLAB's Hall B RICH detector

12 Jun 2018, 14:40
1h 30m
Woodlands Conference Center

Woodlands Conference Center

159 Visitor Center Dr, Williamsburg, VA 23185
Poster presentation Fast Data Transfer Links and Networks Poster 1

Speaker

Mr Cody Dickover (Jefferson Lab)

Description

A fixed latency Serializer-Deserializer(SerDes) is useful in detector electronics for the synchronization and triggering of data acquisition. It is not a common default feature of FPGA transceiver protocol packaging, but it can be custom built by logic in the FPGA fabric.

In this application we have a Xilinx Virtex-5 FPGA driving several GTP fiber transceivers from cards housed in a VXS crate talking to readout boards local to the detector, each hosting a Xilinx Artix-7. This communication runs a 16 bit bus at 125Mhz with a 2.5Gbps line rate.

The transceiver IP cores available on Xilinx parts utilize elastic buffers for various purposes. In order to achieve a fixed latency these buffers must be removed and replaced with custom firmware protocols for communication and link monitoring.

This custom firmware must ensure a stable link on startup, reset or power cycle, and maintain integrity. This includes clock management, word alignment, loss of sync detection, and initial phase alignment.

Minioral Yes
Description FPGA SerDes
Country USA
Speaker Cody Dickover
Institute JLAB

Primary authors

Mr Cody Dickover (Jefferson Lab) Ben Raydo (Jefferson Lab)

Presentation Materials

There are no materials yet.