9-15 June 2018
Woodlands Conference Center
America/New_York timezone
**** See you at Real Time 2020 ****

A 5.5 ps Time-interval RMS Precision Time-to-Digital Convertor Implemented in Intel Arria 10 FPGA

15 Jun 2018, 12:30
20m
Woodlands Conference Center

Woodlands Conference Center

159 Visitor Center Dr, Williamsburg, VA 23185
Oral presentation Front End Fast Detectors 2

Speakers

Mr Jie Kuang (the Department of Modern Physics, University of Science and Technology of China)Prof. Yonggang Wang (the Department of Modern Physics, University of Science and Technology of China)

Description

As an important part of the field programmable gate array (FPGA) market, Intel FPGA has also great potential for implementation of time-to-digital convertor (TDC). In this paper, the basic tapped delay line (TDL) TDC structure is adapted in Intel Arria 10 FPGA, which is manufactured with 20 nm process technology. Because of the serious bubble problem for FPGA made by state-of-art process, the ones counter encoding scheme is employed to maintain the delay elements in TDL resolvable for achieving high TDC time precision. The test of TDC bin width reveals that the characteristics of the delay chain are highly consistent with the fundamental structure of logic resource in the FPGA. To improve TDC time precision, four TDLs are combined parallel for final TDC implementation. Using two identical TDC channels, the average RMS precision for measurements of time-intervals in the range from 0 to 50 ns reaches 5.45 ps. The test results demonstrate that high performance TDC can be implemented in current Intel main-stream FPGAs as well.

Description FPGA-TDC
Speaker Jie Kuang
Institute USTC
Minioral Yes
Country China

Primary author

Mr Jie Kuang (the Department of Modern Physics, University of Science and Technology of China)

Co-author

Prof. Yonggang Wang (the Department of Modern Physics, University of Science and Technology of China)

Presentation Materials

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