Jun 9 – 15, 2018
Woodlands Conference Center
America/New_York timezone
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Design of TDC ASIC based on Temperature Compensation

Jun 14, 2018, 2:35 PM
1h 30m
Woodlands Conference Center

Woodlands Conference Center

159 Visitor Center Dr, Williamsburg, VA 23185
Poster presentation Front End Electronics and Fast Digitizers Poster 2


Ma Yichao


On the basis of requirement of CSNS, we designed a TDC chip with temperature compensation function in this paper, which employed TSMC 180nm process. Using delay unit bufx8 as the major method, delay lines in each level delayed input signal line through the bufx8 unit to realize fundamental measurement function. The time intervals of two fixed delay standard pulses did not change with temperature variation via intra-chip phase-locked loop. After that, the two standard pulses were sent to TDC internal delay line and measured their values. Then the measured values and standard values were compared. According to the result of comparing and decision switch, the structure of delay lines was reconstructed and their levels were recorded at the same time. We could ensure that the total length of the effective delay line were close to clock cycle as much as possible under the current temperature. The chip was tested after the completion of design. It was found that the time resolution of TDC ASIC was 73ps under 1.8V power supply at room temperature while the time resolutions were 103ps and 62ps at 85° and 0°, respectively.

Country China
Minioral Yes
Speaker Ma Yichao
Institute IHEP Beijing
Description Temp compensation

Primary authors


Zhijia SUN (Institute of High Energy Physics, CAS)

Presentation materials