CRU Weekly Meeting

Wednesday 31 Aug 2016, 10:30 → 12:30 Europe/Zurich

CERN

CRU Weekly meeting (31 Aug 2016)

Present: Tivadar, mazsi, Erno

Secretary: Erno(8), PiPPo(5), Shuaib(1), mazsi(3)

Actions:

• We all should read the EDR report prepared by Alex (https://indico.cern.ch/event/512890/attachments/1291308/1954023/20160620CRUEDR.pdf), and delegate the questions to the apropriate persons. The answers should be assembled and presented during the follow up meeting which will be held sometime after the delivery of prototype firmware.
• The loan board is on its way back to the Altera (thanks to Peggy).

Report on Actions:

1. 10G PON

• Still in contact with Altera about the 2UI bitslip issue.
• The TTC PON component is added to the integrated design but not yet connected to the other parts.
• The CTP team received the PON IP from Eduardo and they are working on the integration with the Trigger Emulator. The initial version will be implemented on Kintex 7 so we will be able to use our KC705 board to emulate the LTU and test the communication with the CRU.

2. GBT

• The newly added register based access for the PLLs and XCVRs should be tested before progressing with integration and move the component into the alice-cru GitLab group.
• The loopback test reports zero error even if the reference clock missing (should test the PLL/XCVR lock bits too).
• GBT + SCA integration?
• The currently implemented internal architecture supports only one PLL and up to ~30 XCVR in x1 unbonded mode (using the xN clock lines). It should be extended to support the banking architecture (x6 XVCR + one PLL) as it was in the initial design to impove the timing and the clock distribution performance.

3. DCS

• We started to work with DCS people. The software to connect the DCS to us is ready (first prototype). They have a C-RORC with DCS fake firmware to test the system.

4. PCIe

• Working on a simpler data emulator (PiPPo).
• Once this is tested on hardware I will apply the needed changes to open the DMA to the external word and be able to push data from the GBT using a FIFO like interface (as original planned).
• I will add also extra features to the data emulator: pattern selection, error injection, perf. counter.

5. Integration

• Mazsi is working on an integrated design with TTC PON, GBT-FPGA and PCIe DMA components. The components are not yet interconnected but when this integrated design become buildable then it will allow the independent componet developers to use this design as an application for their components and continue their development in this environment.

AOB

• Sanjoy will travel to CERN on 11th September
• We expect the first PCIe40 from the LHCb at the end of September.
• Prototype FW release is scheduled for end of October which will fit with the arrival of the remaining PCIe40 boards from the LHCb.

Vacations

• PiPPo at CERN in september, on conference 10-14 october, on leave until 7 november (but can work remotely).
• Mazsi working from Budapest 7, 12-13 September, on leave 8-9 September.