Speaker
Description
The LHC is planning an upgrade program which will bring the luminosity up to about 7.5x10$^{34}$cm$^{-2}$s$^{-1}$ in 2027, with the goal of an integrated luminosity of 3000 fb$^{-1}$ by the end of 2037. This High Luminosity scenario, HL-LHC, will present new challenges of higher data rates and increased radiation tolerance for the pixel detector (2x10$^{16}$ neq/cm$^2$, or equivalently 1 Grad, is expected on the inner pixel layer for 3000 fb$^{-1}$ integrated luminosity). To maintain or even improve the performance of the present system, new technologies have to be fully exploited for the so-called Phase-II upgrade. Among them is the future version of front-end chips in 65-nm CMOS by the CERN RD53 Collaboration which supports small pixel sizes of 50x50 or 25x100 μm$^2$ and lower thresholds (~1000 e$^-$). For the development of the appropriate planar pixel sensor, CMS has recently launched a submission of n-in-p sensors on 6 inch wafer with an active thickness of 150 μm at Hamamatsu. The submission consists of physical thinned, direct bonded and deep diffused wafers with p-stop or p-spray isolation. A variety of sensors with and without biasing scheme is designed to match the different read-out chips (RD53A, ROC4Sens, etc.) and first hybrid modules are assembled at Fraunhofer IZM. In this talk, we will present an overview of the Phase II pixel R&D program and report on preliminary results on the HPK submission.
