The 65 nm CMOS technology has been proposed for use in future particle detectors in the upgraded High-Luminosity HLC, where MOS transistors will have to withstand unprecedented total ionizing radiation levels. The strong dependence on geometry, temperature and applied field of the radiation response of this CMOS process has been found to be related to the presence of both STI and spacers oxides. Charge trapped in the spacer oxides modifies the parasitic series resistance, reducing the drive current while the released hydrogen ions (H+) can reach the gate oxide interface and de-passivate Si-H bonds, leading to threshold voltage shifts. Moreover, an unexpected dose-rate sensitivity has been measured in transistors irradiated to high doses. This sensitivity could represent a significant challenge to the definition of a qualification procedure for circuits to be used in extreme radiation environments.